AD9874ABST datasheet(32/40 Pages) AD

32 / 40 page

REV. A

AD9874

–32–

Figure 22b plots the nominal system NF with 16-bit output

data as a function of AGC in both narrow-band and wideband

mode. In wideband mode, the NF curve is virtually unchanged

relative to the 24-bit output data because the output SNR

before truncation is always less than the 96 dB SNR that 16-bit

data can support.

However, in narrow-band mode, where the output SNR

approaches or exceeds the SNR that can be supported with 16-bit

data, the degradation in system NF is more severe. Further-

more, if the signal processing within the DSP adds noise at the

level of an LSB, the system noise figure can be degraded even

more than Figure 22b shows. For example, this could occur in a

fixed 16-bit DSP whose code is not optimized to process the

AD9874’s 16-bit data with minimal quantization effects. To

limit the quantization effects within the AD9874, the 24-bit

data undergoes noise shaping just prior to 16-bit truncation,

thus reducing the in-band quantization noise by 5 dB (with 23

oversampling). This explains why 98.8 dBFS SNR performance

is still achievable with 16-bit data in a 10 kHz BW.

SNR = 98.8dBFS

BW = 50kHz

BW = 150kHz

SNR = 83dBFS

SNR = 94.1dBFS

BW = 10kHz

SNR = 89.9dBFS

VGA ATTENUATION – dB

Figure 22b. Nominal System Noise Figure and Peak SNR

vs. AGCG Setting (fIF = 73.35 MHz, fCLK = 18 MSPS, and

16-bit I/Q data)

APPLICATION CONSIDERATIONS

Frequency Planning

The LO frequency (and/or ADC clock frequency) must be

chosen carefully to prevent known internally generated spurs

from mixing down along with the desired signal, thus degrad-

ing the SNR performance. The major sources of spurs in the

AD9874 are the ADC clock and digital circuitry operating at

1/3 of fCLK. Thus, the clock frequency (fCLK) is the most

important variable in determining which LO (and therefore

IF) frequencies are viable.

Many applications have frequency plans that take advantage of

industry-standard IF frequencies due to the large selection of

low cost crystal or SAW filters. If the selected IF frequency and

ADC clock rate result in a problematic spurious component, an

alternative ADC clock rate should be selected by slightly modi-

fying the decimation factor and CLK synthesizer settings (if

used) such that the output sample rate remains the same. Also,

applications requiring a certain degree of tuning range should

take into consideration the location and magnitude of these

spurs when determining the tuning range as well as optimum IF

and ADC clock frequency.

Figure 23a plots the measured in-band noise power as a func-

tion of the LO frequency for fCLK = 18 MHz and an output

signal bandwidth of 150 kHz when no signal is present. Any LO

frequency resulting in large spurs should be avoided. As this

figure shows, large spurs result when the LO is fCLK/8 = 2.25 MHz

away from a harmonic of 18 MHz (i.e., n fCLK

fCLK/8). Also

problematic are LO frequencies whose odd order harmonics

(i.e., m fLO) mix with harmonics of fCLK to fCLK/8. This spur

mechanism is a result of the mixer being internally driven by a

squared-up version of the LO input consisting of the LO fre-

quency and its odd order harmonics. These spur frequencies

can be calculated from the relation

CLK

=±

()

(12)

where m = 1, 3, 5... and n = 1, 2, 3...

A second source of spurs is a large block of digital circuitry that

is clocked at fCLK/3. Problematic LO frequencies associated with

this spur source are given by:

n f

CLK

(13)

where n = 1, 2, 3 ...

–60

–70

–80

–90

–50

250

300

200

150

100

LO FREQUENCY – MHz

Figure 23a. Total In-Band Noise + Spur Power with No Signal Applied as a Function of the LO Frequency

(fCLK = 18 MHz and Output Signal Bandwidth of 150 kHz)

AD9874ABST датащи(PDF) 32 Page - Analog Devices

AD9874ABST датащи(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL