AD7910ARMZ2 datasheet(19/24 Pages) AD

19 / 24 page

AD7910/AD7920

Rev. C | Page 19 of 24

SERIAL INTERFACE

Figure 23 and Figure 24 show the detailed timing diagram for

serial interfacing to the AD7920 and AD7910, respectively. The

serial clock provides the conversion clock and also controls the

transfer of information from the AD7910/AD7920 during

conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at that point. The conversion is also initiated at this point.

For the AD7920, the conversion requires 16 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in Figure 23 at Point B. On the 16th SCLK falling edge,

the SDATA line goes back into three-state. If the rising edge of

CS occurs before 16 SCLKs have elapsed then the conversion is

terminated and the SDATA line goes back into three-state;

otherwise, SDATA returns to three-state on the 16th SCLK

falling edge, as shown in Figure 23. Sixteen serial clock cycles

are required to perform the conversion process and to access

data from the AD7920.

For the AD7910, the conversion requires 14 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, track-and-

hold goes back into track on the next SCLK rising edge, as

shown in Figure 24 at Point B.

If the rising edge of CS occurs before 14 SCLKs have elapsed, the

conversion is terminated and the SDATA line goes back into

three-state. If 16 SCLKs are used in the cycle, SDATA returns to

three-state on the 16th SCLK falling edge, as shown in Figure 24.

CS going low clocks out the first leading zero to be read in by

the microcontroller or DSP. The remaining data is then clocked

out by subsequent SCLK falling edges beginning with the

second leading zero. Thus, the first falling clock edge on the

serial clock has the first leading zero provided and also clocks

out the second leading zero. The final bit in the data transfer is

valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge.

In applications with a slower SCLK, it is possible to read in data on

each SCLK rising edge. In this case, the first falling edge of SCLK

clocks out the second leading zero, which could be read in the first

rising edge. However, the first leading zero that was clocked out

when CS went low is missed unless it was not read in the first

falling edge. The 15th falling edge of SCLK clocks out the last bit

and it could be read in the 15th rising SCLK edge.

If CS goes low just after the SCLK falling edge has elapsed, CS

clocks out the first leading zero as before, and it can be read on the

SCLK rising edge. The next SCLK falling edge clocks out the sec-

ond leading zero and it could be read on the following rising edge.

SCLK

SDATA

tCONVERT

tQUIET

ZERO

DB11

DB10

DB2

DB1

DB0

THREE-STATE

THREE-

STATE

4 LEADING ZEROS

1/THROUGHPUT

Figure 23. AD7920 Serial Interface Timing Diagram

SCLK

SDATA

tCONVERT

tQUIET

ZERO

DB9

DB8

DB0

ZERO

THREE-STATE

THREE-

STATE

4 LEADING ZEROS

2 TRAILING ZEROS

1/THROUGHPUT

Figure 24. AD7910 Serial Interface Timing Diagram

AD7910ARMZ2 датащи(PDF) 19 Page - Analog Devices

AD7910ARMZ2 датащи(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL