AD7910ARMZ2 datasheet(16/24 Pages) AD

16 / 24 page

AD7910/AD7920

Rev. C | Page 16 of 24

MODES OF OPERATION

The mode of operation of the AD7910/AD7920 is selected by

controlling the logic state of the CS signal during a conversion.

There are two possible modes of operation, normal mode and

power-down mode. The point at which CS is pulled high after

the conversion is initiated determines whether the

AD7910/AD7920 enters power-down mode. Similarly, if the

device is already in power-down mode, CS can control whether

it returns to normal operation or remains in power-down

mode. These modes of operation are designed to provide

flexible power management options. These options can be

chosen to optimize the power dissipation/throughput rate ratio

for different application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance

because the user does not have to worry about any power-up

times; the AD7910/AD7920 remains fully powered all the time.

Figure 19 shows the general diagram of the operation of the

AD7910/AD7920 in this mode.

The conversion is initiated on the falling edge of CS as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times, CS must remain low until

at least 10 SCLK falling edges have elapsed after the falling edge

of CS. If CS is brought high any time after the tenth SCLK

falling edge but before the end of the tCONVERT, then the part

remains powered up but the conversion is terminated and

SDATA goes back into three-state.

For the AD7920, 16 serial clock cycles are required to complete

the conversion and access the complete conversion result. For

the AD7910, a minimum of 14 serial clock cycles is required to

complete the conversion and access the complete conversion

result.

CS can idle high until the next conversion or can idle low until

CS returns high sometime prior to the next conversion,

effectively idling CS low.

Once a data transfer is complete (SDATA has returned to three-

state), another conversion can be initiated after the quiet time,

tQUIET, has elapsed by bringing CS low again.

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered down

between conversions, or a series of conversions can be

performed at a high throughput rate and the ADC is powered

down for a relatively long duration between these bursts of

several conversions. When the AD7910/AD7920 is in power-

down mode, all analog circuitry is powered down.

To enter power-down mode, the conversion process must be

interrupted by bringing CS high anywhere after the second

falling edge of SCLK, and before the tenth falling edge of SCLK,

as shown in Figure 20. Once CS is brought high in this window

of SCLKs, the part enters power-down mode, the conversion

that was initiated by the falling edge of CS is terminated, and

SDATA goes back into three-state. If CS is brought high before

the second SCLK falling edge, the part remains in normal mode

and does not power down. This avoids accidental power-down

due to glitches on the CS line.

To exit this mode of operation and power up the AD7910/

AD7920 again, a dummy conversion is performed. On the falling

edge of CS, the device begins to power up, and continues to

power up as long as CS is held low until after the falling edge of

the tenth SCLK. The device is fully powered up once 16 SCLKs

have elapsed and valid data results from the next conversion, as

shown in Figure 21. If CS is brought high before the tenth SCLK

falling edge, the AD7910/AD7920 goes back into power-down

mode again. This avoids accidental power-up due to glitches on

the CS line or an inadvertent burst of eight SCLK cycles while CS

is low. Although the device can begin to power up on the falling

edge of CS, it powers down again on the rising edge of CS as long

as it occurs before the tenth SCLK falling edge.

POWER-UP TIME

The power-up time of the AD7910/AD7920 is 1 μs, which

means that one dummy cycle is always sufficient to allow the

device to power up. Once the dummy cycle is complete, the

ADC fully powered up and the input signal acquired properly.

The quiet time, tQUIET, must still be allowed from the point

where the bus goes back into three-state after the dummy

conversion, to the next falling edge of CS.

When powering up from the power-down mode with a dummy

cycle, as in Figure 21, the track-and-hold that was in hold mode

while the part was powered down returns to track mode after

the first SCLK edge the part receives after the falling edge of CS.

This is shown as Point A in Figure 21. Although at any SCLK

frequency one dummy cycle is sufficient to power up the device

and acquire VIN, it does not necessarily mean that a full dummy

cycle of 16 SCLKs must always elapse to power up the device

and fully acquire VIN; 1 μs is sufficient to power the device up

and acquire the input signal. Therefore, if a 5 MHz SCLK

frequency is applied to the ADC, the cycle time is 3.2 μs. In one

dummy cycle, 3.2 μs, the part powers up and VIN is fully

acquired. However, after 1 μs with a 5 MHz SCLK, only five

SCLK cycles have elapsed. At this stage, the ADC is fully

powered up and the signal is acquired. In this case, the CS can

be brought high after the tenth SCLK falling edge and brought

low again after a time, tQUIET, to initiate the conversion.

AD7910ARMZ2 датащи(PDF) 16 Page - Analog Devices

AD7910ARMZ2 датащи(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL