AD7910ARMZ2 datasheet(6/24 Pages) AD

6 / 24 page

AD7910/AD7920

Rev. C | Page 6 of 24

TIMING SPECIFICATIONS

VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1

AD7910/AD7920

Limit at TMIN, TMAX

Unit

Description

fSCLK2

kHz min3

MHz max

tCONVERT

14 × tSCLK

AD7910

16 × tSCLK

AD7920

tQUIET

ns min

Minimum quiet time required between bus relinquish and start of next

conversion

ns min

Minimum CS pulse width

ns min

CS to SCLK setup time

t34

ns max

Delay from CS until SDATA three-state disabled

ns max

Data access time after SCLK falling edge

0.4 × tSCLK

ns min

SCLK low pulse width

0.4 × tSCLK

ns min

SCLK high pulse width

t75, 6

SCLK to data valid hold time

ns min

VDD ≤ 3.3 V

9.5

ns min

3.3 V < VDD ≤ 3.6 V

ns min

VDD > 3.6 V

t86, 7

ns max

SCLK falling edge to SDATA three-state

See Note 7

ns min

SCLK falling edge to SDATA three-state

tPOWER-UP8

μs max

Power-up time from full power-down

1 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2 Mark/Space ratio for the SCLK input is 40/60 to 60/40.

3 Minimum fSCLK at which specifications are guaranteed.

4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.

5 Measured with a 50 pF load capacitor.

6 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, shown in the Timing Specifications is the true bus relinquish

time of the part and is independent of the bus loading.

7 T7 values apply to t8 minimum values also.

8 See Power-Up Time section.

200

μAI

200

μAI

1.6V

TO OUTPUT

50pF

Figure 2. Load Circuit for Digital Output Timing Specifications

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