STM32F102XB datasheet(16/80 Pages) STMICROELECTRONICS

16 / 80 page

Description

STM32F102x8, STM32F102xB

16/80

DocID15056 Rev 5

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to

reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It

features:

•

A 24-bit down counter

•

Autoreload capability

•

Maskable system interrupt generation when the counter reaches 0.

•

Programmable clock source

General-purpose timers (TIMx)

There are 3 synchronizable general-purpose timers embedded in the STM32F102xx

medium-density USB access line devices. These timers are based on a 16-bit auto-reload

up/down counter, a 16-bit prescaler and feature 4 independent channels each for input

capture, output compare, PWM or one-pulse mode output. This gives up to 12 input

captures / output compares / PWMs on the LQFP48 and LQFP64 packages.

The general-purpose timers can work together via the Timer Link feature for synchronization

or event chaining. Their counter can be frozen in debug mode.

Any of the general-purpose timers can be used to generate PWM outputs. They all have

independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

I²C bus

Two I²C bus interfaces can operate in multi-master and slave modes. They can support

standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit

addressing in master mode. A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SM Bus 2.0/PM Bus.

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