RXB0D2 datasheet(41/92 Pages) MICROCHIP

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DS21801G-page 41

MCP2515

5.2

Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. Synchronization is

the

process

which

the

DPLL

function

implemented.

When an edge in the transmitted data is detected, the

logic will compare the location of the edge to the

expected time (SyncSeg). The circuit will then adjust

the values of PS1 and PS2 as necessary.

There are two mechanisms used for synchronization:

Hard synchronization

Resynchronization

5.2.1

HARD SYNCHRONIZATION

Hard synchronization is only performed when there is a

recessive-to-dominant edge during a BUS IDLE

condition, indicating the start of a message. After hard

synchronization, the bit time counters are restarted with

SyncSeg.

Hard synchronization forces the edge that has

occurred to lie within the synchronization segment of

the

restarted

bit

time.

Due

the

rules

synchronization, if a hard synchronization occurs, there

will not be a resynchronization within that bit time.

5.2.2

RESYNCHRONIZATION

As a result of resynchronization, PS1 may be

lengthened or PS2 may be shortened. The amount of

lengthening or shortening of the phase buffer segments

has an upper-bound, given by the Synchronization

Jump Width (SJW).

The value of the SJW will be added to PS1 or

subtracted from PS2 (see Figure 5-3). The SJW

represents the loop filtering of the DPLL. The SJW is

programmable between 1 TQ and 4 TQ.

5.2.2.1

Phase Errors

The NRZ bit coding method does not encode a clock

into the message. Clocking information will only be

derived from recessive-to-dominant transitions. The

property which states that only a fixed maximum

number of successive bits have the same value (bit-

stuffing) ensures resynchronization to the bit stream

during a frame.

The phase error of an edge is given by the position of

the edge relative to SyncSeg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

•e = 0 if the edge lies within SYNCSEG

•e > 0 if the edge lies before the SAMPLE POINT

(TQ is added to PS1)

•e < 0 if the edge lies after the SAMPLE POINT of

the previous bit (TQ is subtracted from PS2)

5.2.2.2

No Phase Error (e = 0)

If the magnitude of the phase error is less than or equal

to the programmed value of the SJW, the effect of a

resynchronization is the same as that of a hard

synchronization.

5.2.2.3

Positive Phase Error (e > 0)

If the magnitude of the phase error is larger than the

SJW and, if the phase error is positive, PS1 is

lengthened by an amount equal to the SJW.

5.2.2.4

Negative Phase Error (e < 0)

If the magnitude of the phase error is larger than the

resynchronization jump width and the phase error is

negative, PS2 is shortened by an amount equal to the

SJW.

5.2.3

SYNCHRONIZATION RULES

Only recessive-to-dominant edges will be used

for synchronization.

Only one synchronization within one bit time is

allowed.

An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge.

A transmitting node will not resynchronize on a

positive phase error (e > 0).

If the absolute magnitude of the phase error is

greater than the SJW, the appropriate phase

segment will adjust by an amount equal to the

SJW.

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