SO16N datasheet(20/51 Pages) STMICROELECTRONICS

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Application information

L6566BH

20/51

Doc ID 16610 Rev 2

turn-off to prevent any negative-going edge that follows leakage inductance

demagnetization from triggering the ZCD circuit erroneously.

The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the

internal diagram of the ZCD block of

Figure 8. The upper clamp is typically located at 5.7 V,

while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary

winding is a resistor divider. Its resistance ratio is properly chosen (see

Section 5.11: OVP

block) and the individual resistance values (RZ1, RZ2) are such that the current sourced and

sunk by the pin is within the rated capability of the internal clamps (

± 3 mA).

At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up

the system. The oscillator is programmed externally by means of a resistor (RT) connected

from the OSC pin (13) to ground. With good approximation the oscillation frequency fosc is:

Equation 2

(with fosc in kHz and RT in kΩ). As the device is turned on, the oscillator starts immediately;

at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is

turned on, therefore starting the first switching cycle right at the beginning of the second

oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the

current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the

transformer starts demagnetization. If this completes (so a negative-going edge appears on

the ZCD pin) after a time exceeding one oscillation period Tosc = 1/fosc from the previous

turn-on, the MOSFET is turned on again – with some delay to ensure minimum voltage at

turn-on – and the oscillator ramp is reset. If, on the other hand, the negative-going edge

appears before Tosc has elapsed, it is ignored and only the first negative-going edge after

Tosc turns on the MOSFET and synchronizes the oscillator. In this way one or more drain

ringing cycles are skipped (“valley-skipping mode”,

Figure 9) and the switching frequency is

prevented from exceeding fosc.

Note:

When the system operates in valley skipping-mode, uneven switching cycles may be

observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET

is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for

cycle-by-cycle energy balance may fall in between. Therefore, one or more longer switching

cycles is compensated by one or more shorter cycles and vice versa. However, this

mechanism is absolutely normal and there is no appreciable effect on the performance of

the converter or on its output voltage.

osc

⋅

≈

Figure 9.

Drain ringing cycle skipping as the load is gradually reduced

Pin = Pin'

(limit condition)

Pin = Pin'' < Pin'

Pin = Pin''' < Pin''

VDS

TFW

Tosc

TON

VDS

Tosc

VDS

Tosc

AM11485v1

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