ADDI7100

Rev. C | Page 14 of 20

APPLICATIONS INFORMATION

The ADDI7100 is a complete analog front-end (AFE) product

for digital still camera and camcorder applications. As shown in

Figure 14, the CCD image (pixel) data is buffered and sent to

the ADDI7100 analog input through a series input capacitor.

The ADDI7100 performs the dc restoration, CDS sampling,

gain adjustment, black level correction, and analog-to-digital

conversion. The digital output data of the ADDI7100 is then

processed by the image processing ASIC. The internal registers

of the ADDI7100—used to control gain, offset level, and other

functions—are programmed by the ASIC or by a microprocessor

through a 3-wire serial digital interface. A system timing generator

provides the clock signals for both the CCD and the AFE (see

Figure 14).

CCD

CCDIN

BUFFER

ADDI7100

REGISTER

DATA

SERIAL

INTERFACE

DIGITAL

OUTPUTS

DIGITAL IMAGE

PROCESSING

ASIC

TIMING

GENERATOR

V-DRIVER

CCD

TIMING

CDS/CLAMP

TIMING

Figure 14. System Applications Diagram

24

REFB

23

REFT

22

CCDIN

21 AVSS

D2

1

D3

2

D0

D1

D4

3

20 AVDD

19

SHD

18

SHP

17

CLPOB

D5

4

D6

5

D7

6

D8

7

D9

8

DATA

OUTPUTS

12

910

3V

DRIVER

SUPPLY

3V

ANALOG

SUPPLY

3V

ANALOG

SUPPLY

12 13 14 15 16

5

CLOCK

INPUTS

3

SERIAL

INTERFACE

CCDIN

ADDI7100

TOP VIEW

(Not to Scale)

1.0µF

1.0µF

0.1µF

0.1µF

0.1µF

0.1µF

NC = NO CONNECT (NOT INTERNALLY CONNECTED, MAY BE TIED TO GROUND OR LEFT FLOATING).

PIN 1

IDENTIFIER

32 31 30 29 28 27 26 25

11

VD OUTPUT FROM ASIC/DSP

(SHOULD BE GROUNDED IF NOT USED.)

Figure 15. Recommended Circuit Configuration for CCD Mode