ADDI7100

Rev. C | Page 5 of 20

TIMING SPECIFICATIONS

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period

22

ns

DATACLK High/Low Pulse Width

9

11

ns

SHP Pulse Width

5.5

ns

SHD Pulse Width

5.5

ns

CLPOB Pulse Width1

2

20

Pixels

SHP Rising Edge to SHD Falling Edge

5.5

ns

SHP Rising Edge to SHD Rising Edge

9

11

ns

SHD Rising Edge to SHP Rising Edge

9

11

ns

SHD Rising Edge to SHP Falling Edge

5.5

ns

Internal Clock Delay

4

ns

DATA OUTPUTS

Output Delay

15

ns

Pipeline Delay

15

Cycles

SERIAL INTERFACE

Maximum SCK Frequency (Must Not Exceed Pixel Rate)

40

MHz

SL to SCK Setup Time

10

ns

SCK to SL Hold Time

10

ns

SDATA Valid to SCK Rising Edge Setup

10

ns

SCK Rising Edge to SDATA Valid Hold

10

ns

Timing Diagrams

PIXEL N

PIXEL

N + 1

PIXEL

N + 2

PIXEL

N + 14

PIXEL

N + 15

N – 15

N – 14

N – 13

N – 1

N

NOTES

1. RECOMMENDED PLACEMENT FOR DATACLK RISING (ACTIVE) EDGE IS NEAR THE SHP OR SHD RISING

(ACTIVE) EDGE. THE BEST LOCATION FOR LOWEST NOISE WILL BE SYSTEM DEPENDENT.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

SHP

SHD

DATACLK

OUTPUT

DATA

CCD

SIGNAL

(CCDIN)

Figure 3. CCD Sampling Timing (Default Polarity Settings)