ADDI7100

Rev. C | Page 8 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

24 REFB

23 REFT

22 CCDIN

21 AVSS

D2 1

D3 2

D4 3

20 AVDD

19 SHD

18 SHP

17 CLPOB

D5 4

D6 5

D7 6

D8 7

D9 8

NOTES

1. IT IS RECOMMENDED THAT THE EXPOSED

PAD BE SOLDERED TO THE GROUND PLANE

OF THE PCB.

2. NC = NO CONNECT.

ADDI7100

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1 to 10

D2 to D11

DO

Digital Data Outputs.

11

DRVDD

P

Digital Output Driver Supply.

12

DRVSS

P

Digital Output Driver Ground.

13

DVDD

P

Digital Supply.

14

DATACLK

DI

Digital Data Output Latch Clock.

15

DVSS

P

Digital Supply Ground.

16

PBLK

DI

Preblanking Clock Input.

17

CLPOB

DI

Black Level Clamp Clock Input.

18

SHP

DI

CDS Sampling Clock for CCD Reference Level.

19

SHD

DI

CDS Sampling Clock for CCD Data Level.

20

AVDD

P

Analog Supply.

21

AVSS

P

Analog Ground.

22

CCDIN

AI

Analog Input for CCD Signal.

23

REFT

AO

ADC Top Reference Voltage Decoupling.

24

REFB

AO

ADC Bottom Reference Voltage Decoupling.

25

SL

DI

Serial Digital Interface Load Pulse.

26

SDATA

DI

Serial Digital Interface Data Input.

27

SCK

DI

Serial Digital Interface Clock Input.

28

VD

DI

Vertical Sync Input. Controls the update time of VD-updated registers. If this pin is not

needed, it should be tied to GND.

29, 30

NC

NC

Not Internally Connected.

31, 32

D0, D1

DO

Digital Data Output.