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MPC8315 датащи(PDF) 5 Page - Freescale Semiconductor, Inc

номер детали MPC8315
подробное описание детали  MPC8315E PowerQUICC II Pro Processor Hardware Specifications
PDF  106 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8315 датащи(HTML) 5 Page - Freescale Semiconductor, Inc

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MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
MPC8315E Features
•
Signal (RCK) can be configured as either input or output
•
Frame sync and data signals can be programmed to be sampled either on the rising edge or on the
falling edge of the clock
•
Frame sync can be programmed as active low or active high
•
Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame
•
MSB or LSB first support
2.7
USB Dual-Role Controller
The USB controller includes the following features:
•
Designed to comply with USB Specification, Rev. 2.0
•
Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
•
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
•
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation.
Low-speed operation is supported only in host mode.
•
Supports UTMI+ low pin interface (ULPI) or on-chip USB-2.0 full-speed/high-speed PHY
•
Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI PHY
2.8
Dual PCI Express Interfaces
The PCI Express interfaces have the following features:
•
PCI Express 1.0a compatible
•
x1 link width
•
Selectable operation as root complex or endpoint
•
Both 32- and 64-bit addressing
•
128-byte maximum payload size
•
Support for MSI and INTx interrupt messages
•
Virtual channel 0 only
•
Selectable Traffic Class
•
Full 64-bit decode with 32-bit wide windows
•
Dedicated descriptor based DMA engine per interface with separate read and write channels



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