SPEAR320-2 datasheet(71/73 Pages) STMICROELECTRONICS

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SPEAr320

Revision history

Doc ID 16755 Rev 5

71/73

02-Feb-2010

2 (continued)

Changed the baud rate for the UARTs with Hardware flow control

from “up to 460.8 Kbaud” into “up to 3 Mbps”.

Table 15: Reconfigurable array subsystem memory map: changed a

typo error “UART23” into “UART2”.

Section 3.10: CAN controller: changed “32 message objects (132 x

32 message RAM)” to “16 message objects (136 x 16 message

RAM)”.

Corrected a typo error in the Figure 13: In/out data address signal

waveforms for NAND Flash and Figure 16: In/out data signal

waveforms for 16-bit NAND Flash configuration.

Updated Table 4: Power supply pin description and added a note at

the end of the table.

Corrected the voltage capable of RTC in the Table 3: Master clock,

RTC, Reset and 3.3 V comparator pin descriptions.

Updated figures of Section 7.6: FSMC timing characteristics.

Updated Figure 19: MII TX waveforms, Figure 26: Block diagram of

MII TX pins, Figure 20: MII RX waveforms

Corrected the speed of UART1 and UART2 in Section 3.18.2:

UART1 from “5 Mbps” into “6 Mbps”.

Updated Table 3: Master clock, RTC, Reset and 3.3 V comparator

pin descriptions, Table 7: USB pin description andTable 9: DDR pin

description

Minor text corrections.

18-Nov-2010

Corrected pin assignment of UART0_RTS and CTS in Table 11:

PL_GPIO multiplexing scheme

Added Section 7.14: ADC characteristics

Changed max. speed of UART2 and UART3 in feature descriptions

from 6 Mbps to 7 Mbps and updated Table 50: UART transmit timing

characteristics on page 66.

02-Dec-2010

Corrected SRAM size from 56 K to 8 Kbytes in Chapter 2: Main

features

Updated feature descriptions for the 3 UARTs in Section 3.18:

UARTs

Table 55.

Document revision history (continued)

Date

Revision

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