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SPEAR320-2 датащи(PDF) 64 Page - STMicroelectronics

номер детали SPEAR320-2
подробное описание детали  Embedded MPU with ARM926 core, optimized for factory automation and consumer applications
PDF  73 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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SPEAR320-2 датащи(HTML) 64 Page - STMicroelectronics

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Timing requirements
SPEAr320
64/73
Doc ID 16755 Rev 5
7.12.1
SPI master mode timings (clock phase = 0)
Figure 25.
SPI master mode external timing (clock phase = 0)
Table 46.
Timing requirements for SPI master mode (clock phase = 0)
No.
Parameters
Min
Max
Unit
4tsu(DIV-CLKL)
Setup time, MISO (input) valid before
SSP_CLK (output) falling edge
Clock
polarity = 0
-0.4
-0.3
ns
5tsu(DIV-CLKH)
Setup time, MISO (input) valid before
SSP_CLK (output) rising edge
Clock
polarity = 1
-0.4
-0.3
ns
6th(CLKL-DIV)
Hold time, MISO (input) valid after
SSP_CLK (output) falling edge
Clock
polarity = 0
0.9
1.7
ns
7th(CLKH-DIV)
Hold time, MISO (input) valid after
SSP_CLK (output) rising edge
Clock
polarity = 1
0.9
1.7
ns
Table 47.
Switching characteristics over recommended operating conditions for
SPI master mode (clock phase =0 )
No.
Parameters
Min
Max
Unit
8td(CLKH-DOV)
Delay time, SSP_CLK (output) rising
edge to MOSI (output) transition
Clock
Polarity = 0
-3.1
2.2
ns
9td(CLKL-DOV)
Delay time, SSP_CLK (output) falling
edge to MOSI (output) transition
Clock
Polarity = 1
-3.1
2.2
ns
10
td(ENL-CLKH/L)
Delay time, SSP_CSn (output) falling edge to first
SSP_CLK (output) rising or falling edge
Tns
11
td(CLKH/L-ENH)
Delay time, SSP_CLK (output) rising or falling edge
to SSP_CSn (output) rising edge
T/2
ns
SSP_CSn
SSP_SCLK
(Clock Polarity = 0)
SSP_SCLK
(Clock Polarity = 1)
SSP_MISO
(Input)
SSP_MOSI
(Output)



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