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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FX3 датащи(PDF) 24 Page - Cypress Semiconductor |
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FX3 датащи(HTML) 24 Page - Cypress Semiconductor |
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24 / 45 page  CYUSB301X Document Number: 001-52136 Rev. *N Page 24 of 45 AC Timing Parameters GPIF II Timing Figure 9. GPIF II Timing in Synchronous Mode - CT L (O U T) CT L( IN) tS tH tD H tD S tC LK CLK tC T LO tC O E Data(IN) Data 1 (O U T) tH Z tLZ tD O H tC O H tC LK H tC LK L tLZ Data 2 (O U T) tC O tD O H D Q [31:0] Table 9. GPIF II Timing Parameters in Synchronous Mode [4] Parameter Description Min Max Units Frequency Interface clock frequency – 100 MHz tCLK Interface clock period 10 – ns tCLKH Clock high time 4 – ns tCLKL Clock low time 4 – ns tS CTL input to clock setup time 2 – ns tH CTL input to clock hold time 0.5 – ns tDS Data in to clock setup time 2 – ns tDH Data in to clock hold time 0.5 – ns tCO Clock to data out propagation delay when DQ bus is already in output direction –8 ns tCOE Clock to data out propagation delay when DQ lines change to output from tristate and valid data is available on the DQ bus -9 tCTLO Clock to CTL out propagation delay – 8 ns tDOH Clock to data out hold 2 – ns tCOH Clock to CTL out hold 0 – ns tHZ Clock to high-Z – 8 ns tLZ Clock to low-Z 0 – ns Note 4. All parameters guaranteed by design and validated through characterization. |
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