TMS320_13 datasheet(9/70 Pages) TI1

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TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

 HOUSTON, TEXAS 77001

interrupts and subroutines

The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that

interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),

and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest

priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on

two-word boundaries so that branch instructions can be accommodated in those locations if desired.

A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle

instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to

instructions that are repeated and to instructions that become multicycle due to the READY signal.

external interface

The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address

spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by

having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the

processor’s external address and data buses in the same manner as memory-mapped devices. Interface to

memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are

made with slower devices, the TMS320C2x processor waits until the other device completes its function and

signals the processor via the READY line. Then, the TMS320C2x continues execution.

A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and

other serial systems. The interface signals are compatible with codecs and many other serial devices with a

minimum of external hardware. The serial port may also be used for intercommunication between processors

in multiprocessing applications.

The serial port has two memory-mapped registers: the data transmit register (DXR) and the data receive register

(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same

manner as any other data memory location. Each register has an external clock, a framing synchronization

pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one

device to transmit while the others are in the receive mode. The serial port on the TMS320C25 is double-buffered

and fully static.

multiprocessing

The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can

be used as follows:

 A standalone processor

 A multiprocessor with devices in parallel

 A slave/host multiprocessor with global memory space

 A peripheral processor interfaced via processor-controlled signals to another device.

For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space

and communicating with that space via the BR (bus request) and READY control signals. Global memory is data

memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit

memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x’s data memory

as global external memory. The contents of the register determine the size of the global memory space. If the

current instruction addresses an operand within that space, BR is asserted to request control of the bus. The

length of the memory cycle is controlled by the READY line.

The TMS320C2x supports DMA (direct memory access) to its external program/data memory using the HOLD

and HOLDA signals. Another processor can take complete control of the TMS320C2x’s external memory by

asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a

high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may

proceed concurrently when the device is in the hold mode.

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