TMS320_13 datasheet(32/70 Pages) TI1

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TMS320 SECOND GENERATION

DIGITAL SIGNAL PROCESSORS

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

 HOUSTON, TEXAS 77001

SERIAL PORT TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER

MIN

TYP

MAX

UNIT

td(CH-DX)

DX valid after CLKX rising edge (see Note 10)

td(FL-DX)

DX valid after FSX falling edge (TXM = 0, see Note 10)

td(CH-FS)

FSX valid after CLKX rising edge (TXM = 1)

NOTES: 3. Q = 1/4tc(C).

10. The last occurrence of FSX falling and CLKX rising.

timing requirements over recommended operating conditions (see Note 3)

MIN

NOM

MAX

UNIT

tc(SCK)

Serial port clock (CLKX/CLKR) cycle time†

200

tf(SCK)

Serial port clock (CLKX/CLKR) fall time

25‡

tr(SCK)

Serial port clock (CLKX/CLKR) rise time

25‡

tw(SCK)

Serial port clock (CLKX/CLKR) low pulse duration (see Note 11)

tw(SCK)

Serial port clock (CLKX/CLKR) high pulse duration (see Note 11)

tsu(FS)

FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)

th(FS)

FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)

tsu(DR)

DR setup time before CLKR falling edge

th(DR)

DR hold time after CLKR falling edge

† The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down

to fsx =0Hz.

‡ Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

11. The duty cycle of the serial port clock must be within 40-60%.

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