TMS320_13 datasheet(63/70 Pages) TI1

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TMS320E25

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

 HOUSTON, TEXAS 77001

Table 6. TMS320E25 Protect and Verify EPROM Mode Levels

SIGNAL†

TMS320E25 PIN

TMS27C64 PIN

ROM PROTECT

PROTECT VERIFY

VIH

VIL

VIH

VIL

PGM

VIH

VPP

VCC

61,35

VCC + 1

VCC

VSS

10, 27, 44

VSS

CLKIN

VSS

EPT

VPP

Q8-Q1

18-11

11-13, 15-19

Q8 = PULSE

Q8 = RBIT

A12-A10

40-38

2, 23, 21,

A9-A7

37, 36, 34

24, 25, 3

VIL

VIH

A3-A0

30-28, 26

7-10

† In accordance with TMS27C64.

LEGEND;

VIH = TTL high level; VIL = TTL low level; VCC =5V  0.25 V

VPP = 12.5 V  0.5 V; X = don’t care

PULSE = low-going TTL level pulse; RBIT = ROM protect bit.

EPROM protect

The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security

of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM

protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed,

disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once

programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby

maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM

protect cycle, which consists of setting the E,G,PGM, and A4 pins high, VPP and EPT to 2.5 V  0.5 V, and

pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the

flowchart of Figure 12. The required setups in the figure are detailed in Table 6.

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