TAS5707APHPR datasheet(6/58 Pages) TI1

6 / 58 page

TAS5707, TAS5707A

SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009

www.ti.com

PIN FUNCTIONS

TYPE

5-V

TERMINATION

DESCRIPTION

(1)

TOLERANT

(2)

NAME

NO.

AGND

Analog ground for power stage

AVDD

3.3-V analog power supply

AVSS

Analog 3.3-V supply ground

BST_A

High-side bootstrap supply for half-bridge A

BST_B

High-side bootstrap supply for half-bridge B

BST_C

High-side bootstrap supply for half-bridge C

BST_D

High-side bootstrap supply for half-bridge D

DVDD

3.3-V digital power supply

DVSSO

Oscillator ground

DVSS

Digital ground

FAULT

Backend error indicator. Asserted LOW for over temperature, over

current, over voltage, and under voltage error conditions. De-asserted

upon recovery from error condition.

GND

Analog ground for power stage

GVDD_OUT

5, 32

Gate drive internal regulator output

LRCLK

5-V

Pulldown

Input serial audio data left/right clock (sample rate clock)

MCLK

5-V

Pulldown

Master clock input

–

No connection

OC_ADJ

Analog overcurrent programming. Requires resistor to ground.

OSC_RES

Oscillator trim resistor. Connect an 18.2-k

Ω 1% resistor to DVSSO.

OUT_A

Output, half-bridge A

OUT_B

Output, half-bridge B

OUT_C

Output, half-bridge C

OUT_D

Output, half-bridge D

PDN

5-V

Pullup

Power down, active-low. PDN prepares the device for loss of power

supplies by shutting down the noise shaper and initiating PWM stop

sequence.

PGND_AB

47, 48

Power ground for half-bridges A and B

PGND_CD

37, 38

Power ground for half-bridges C and D

PLL_FLTM

PLL negative loop filter terminal

PLL_FLTP

PLL positive loop filter terminal

PVDD_A

2, 3

Power supply input for half-bridge output A

PVDD_B

44, 45

Power supply input for half-bridge output B

PVDD_C

40, 41

Power supply input for half-bridge output C

PVDD_D

34, 35

Power supply input for half-bridge output D

RESET

5-V

Pullup

Reset, active-low. A system reset is generated by applying a logic low

to this pin. RESET is an asynchronous control signal that restores the

DAP to its default conditions, and places the PWM in the hard mute

state (tristated).

SCL

5-V

I2C serial control clock input

SCLK

5-V

Pulldown

Serial audio data clock (shift clock). SCLK is the serial audio port input

data bit clock.

SDA

DIO

5-V

I2C serial control data interface input/output

SDIN

5-V

Pulldown

Serial audio data input. SDIN supports three discrete (stereo) data

formats.

(1)

TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2)

All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic

levels if the pins are left unconnected (pullups

→ logic 1 input; pulldowns → logic 0 input).

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