TAS5707APHPR datasheet(33/58 Pages) TI1

33 / 58 page

TAS5707, TAS5707A

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SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009

Normal Operation

The following are the only events supported during normal operation:

(a) Writes to master/channel volume registers

(b) Writes to soft mute register

(d) Clock errors and rate changes

Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup

ramp (where Tstart is specified by register 0x1A).

Shutdown Sequence

Enter:

Ensure I2S clocks have been stable and valid for at least 50ms.

Write 0x40 to register 0x05.

Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A).

Once in shutdown, stable clocks are not required while device remains idle.

If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before

returning to step 4 of initialization sequence.

Exit:

Ensure I2S clocks have been stable and valid for at least 50ms.

Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms

after trim following AVDD/DVDD powerup ramp).

Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A).

Proceed with normal operation.

Powerdown Sequence

Use the following sequence to powerdown the device and its supplies:

If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,

assert PDNZ=0 and wait at least 2ms.

Assert RESETZ=0.

Drive digital inputs low and ramp down PVDD supply as follows:

•

Drive all digital inputs low after RESETZ has been low for at least 2us.

•

Ramp down PVDD while ensuring that it remains above 8V until RESETZ has been low for at

least 2us.

Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and

that it is never more than 2.5V below the digital inputs.

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