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SN75970B2DGG датащи(PDF) 18 Page - Texas Instruments

номер детали SN75970B2DGG
подробное описание детали  SCSI DIFFERENTIAL CONVERTER-CONTROL
PDF  23 Pages
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производитель  TI [Texas Instruments]
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SN75970B2DGG датащи(HTML) 18 Page - Texas Instruments

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SN75970B
SCSI DIFFERENTIAL CONVERTER-CONTROL
SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The third possible flow is that a device on the B side won the arbitration and is selecting or reselecting another
device on the B side. DSEL_LATCH is set, and 400 ns of BBSY is asserted first by the object of the selection
or reselection. Since ASEL is still asserted, the controller remains in the select 1 state throughout the selection
or reselection. If the BBSY deassertion is missed by the timer, again the controller remains in the select 1 state.
Once the transfer state is entered, BBSY is asserted and BSEL is dropped. This again returns the controller
to a select 1 state. At the end of the transfer both BBSY and BSEL are deasserted. After the timer limit is reached,
the controller goes to the arbitration state for the next bus arbitration.
The controller enters the select 2 state (see Figure 9) during the selection or reselection phases when the
initiator and terminator are on the opposite side of SDCC. In this state the RESEL_LATCH is closed, capturing
the value of the I/O. When RESEL_LATCH is one, reselection is indicated. When RESEL_LATCH equals zero,
a selection is indicated. RESEL_LATCH, along with the DSEL_LATCH, now defines which side the initiator is
on and therefore what direction to establish for all the bus signals. The target must be on the other side; if both
target and initiator were on the B side, the select 2 state would never be entered.
When the RESEL_LATCH is zero, indicating a selection, the connection is not made. When DSEL_LATCH is
one, the initiator is on the B side and the control lines it drives have their A side drivers enabled. These terminals
are the initiator group of ACK and ATN along with SEL. The other terminals are driven by the target and have
the B side drivers enabled. They are the target group of REQ, MSG, C/D, and I/O, along with BSY. When
DSEL_LATCH is zero the connection is reversed. Since transfer states are not started, DRVBUS is set to 1,
indicating that the data transceiver chips should not take their direction control from SDB and should be actively
negated. SDB is generated from I/O and is the bus signal that determines data transfer direction. In this case
it indicates the selection phase, the controller immediately transfers to the transfer state, where exactly the same
actions are done.
When the RESEL_LATCH is 1 indicating a reselection, there are one or more actions before information states
can be entered. When the target reselects the initiator, the initiator responds by asserting BSY. Once the
connection is made, the assertion of BSY must be changed over to the target, and the controller must reverse
the BSY driver direction. It does this when SEL deasserts by transferring to the transfer state where the BSY
direction is reversed. In the select 2 state all the control line directions are set as appropriate, except that
DRVBUS is not yet asserted. In the transfer state DRBVUS is set as well.
The controller remains in the transfer state during all other SCSI states. When a bus free state is detected, it
goes back to the arbitration state to wait for the next activity. Note that after BBSY and BSEL deassert, the
controller continues to actively drive the control lines and the data lines through DRVBUS until 400 ns of
continuous deassertion is detected. The drivers are turned off only when the state change occurs.
Figure 10 shows a typical system configuration. The timeout function used in the arbitration state is
implemented with a resistor and capacitor connected to the TIMEOUT terminal. During reset and whenever the
timer is not in use, the terminal is driven to VCC. The timer starts when the driver turns off, allowing the capacitor
to charge and the TIMEOUT terminal to drop to ground. When VIT- is reached, the driver turns on, discharging
the capacitor and returning TIMEOUT to VCC. A timeout event is declared after the driver turns back on and
TIMEOUT exceeds VIT+.
RST can be asserted on either the A or B side, and is driven to the other side. The drive to the other side is
controlled by a bidirectional latch. When one side asserts, the other side is asserted and a latch is set to that
direction. When the first side deasserts, the driver turns off, but the direction is held until both sides are
deasserted. Only then can the direction change.



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