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SN75970B2DGG датащи(PDF) 16 Page - Texas Instruments |
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SN75970B2DGG датащи(HTML) 16 Page - Texas Instruments |
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16 / 23 page ![]() SN75970B SCSI DIFFERENTIAL CONVERTER-CONTROL SLLS323A – NOVEMBER 1999 – REVISED JANUARY 2000 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION To correctly set the direction of the SCSI bus signals, the SN75970B must follow the activity on the bus. An asynchronous, 5-state controller watches the state of all the bus control signals, sets the direction of each control signal as needed, and generates the DRVBUS and SDB outputs to control one or two external SN75971B SCSI differential converter-data devices. The controller never generates the data driven on a bus signal; it only enables the drivers. The clock input implements a 400-ns timer that is not part of the controller itself. Controller-state transitions occur immediately when all the transition conditions are met. Note that the frequency of the supplied clock, either 20 MHz or 40 MHz, must be correct in order to meet the SCSI specifications. As shown in Figure 8, after reset, the controller begins in the bus free state. In case the controller was attached to an active differential bus, it waits for the SCSI bus free condition, defined as when BBSY and BSEL are deasserted for 400 ns. While waiting for the SCSI bus free condition, the state of BBSY and BSEL passes through to the A side. The A side bus device cannot take part in bus activity during this condition before the SCSI bus free condition. Once SCSI bus free is detected, the SCSI arbitration state is entered. Both ABSY and BBSY are enabled; thus when either signal asserts, both drivers turn on and both signals remain asserted until this state is left. Normally the SCSI arbitration state ends after the winner of arbitration asserts BSEL. This would cause the controller to go to the select 1 state. However, when BSEL is not asserted, a timeout would eventually be detected and cause a reset of the controller. In the select 1 state two latches are open, DSEL_LATCH and RESEL_LATCH. The first latch captures the state of BSEL so that following states can determine whether the arbitration winner was on the A side or B side. |
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