64GA110 datasheet(57/330 Pages) MICROCHIP

57 / 330 page

 2010 Microchip Technology Inc.

DS39905E-page 57

PIC24FJ256GA110 FAMILY

5.0

FLASH PROGRAM MEMORY

The PIC24FJ256GA110 family of devices contains

internal Flash program memory for storing and execut-

ing application code. The memory is readable, writable

and erasable when operating with VDD over 2.35V. If

the regulator is disabled, the VDDCORE voltage must be

over 2.25V.

Flash memory can be programmed in three ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self-Programming (RTSP)

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

ICSP allows a PIC24FJ256GA110 family device to be

serially programmed while in the end application circuit.

This is simply done with two lines for the programming

clock and programming data (which are named PGECx

and PGEDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

RTSP is accomplished using TBLRD (table read) and

TBLWT

(table write) instructions. With RTSP, the user

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

5.1

Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using the TBLPAG<7:0> bits and the Effective

Address (EA) from a W register specified in the table

instruction, as shown in Figure 5-1.

The TBLRDL and the TBLWTL instructions are used to

read or write to bits<15:0> of program memory.

TBLRDL

and TBLWTL can access program memory in

both Word and Byte modes.

The TBLRDH and TBLWTH instructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTH can also access program memory in Word

or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information, refer to the

“PIC24F

Family

Reference

Manual”

Section

“Program

Memory”

(DS39715).

Program Counter

24 Bits

Program

TBLPAG Reg

8 Bits

Working Reg EA

16 Bits

Using

Byte

24-Bit EA

1/0

Select

Table

Instruction

Counter

Using

User/Configuration

Space Select

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