MPC930 MPC931

MOTOROLA

TIMING SOLUTIONS

BR1333 — Rev 6

12

Figure 17. Single versus Dual Waveforms

TIME (nS)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 18 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

Figure 18. Optimized Dual Line Termination

7

Ω

MPC930/931

OUTPUT

BUFFER

RS = 36Ω

ZO = 50Ω

RS = 36Ω

ZO = 50Ω

7

Ω + 36Ω k 36Ω = 50Ω k 50Ω

25

Ω = 25Ω

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.