MPC930 MPC931

TIMING SOLUTIONS

BR1333 — Rev 6

5

MOTOROLA

MPC930 AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

fxtal

Crystal Oscillator Frequency Range

10

20

MHz

Note 5., Note 7.

fref

Input Reference Frequency

Note 7.

Note 7.

MHz

Ref = TCLK

tos

Output–to–Output Skew

Same Frequency

(Note 4.)

Diff Frequency

Same Frequency

Diff Frequency

200

300

300

450

300

400

400

600

ps

fmax ≤ 100MHz

fmax ≤ 100MHz

fmax > 100MHz

fmax > 100MHz

fVCO

VCO Lock Range

Power_Dn = 0

Power_Dn = 1

100

50

280

140

MHz

fmax

Maximum Output Frequency

Qa, Qb (

÷2)

Qa, Qb, Qc (

÷4)

Qc (

÷6)

140

80

47

MHz

Note 4.

tpd

TCLK to EXT_FB Delay

–600

–100

400

ps

fref = 50MHz, FB = ÷4

tpw

Output Duty Cycle (Note 4.)

tCYCLE/2

–750

tCYCLE/2

±500

tCYCLE/2

+750

ps

tr, tf

Output Rise/Fall Time (Note 4.)

0.1

1.0

ns

0.8 to 2.0V

tPLZ, tPHZ

Output Disable Time

2.0

8.0

ns

50

Ω to VCC/2

tPZL

Output Enable Time

2.0

10

ns

50

Ω to VCC/2

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

±100

ps

Note 6.

tlock

Maximum PLL Lock Time

10

ms

4. Measured with 50

Ω to VCC/2 termination.

5. See Applications Info section for more Crystal specifications.

6. See Applications Info section for more jitter information.

7. Input reference frequency is bounded by VCO lock range and feedback divide selection.

MPC931 AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

fref

Input Reference Frequency

Note 11.

Note 11.

MHz

tos

Output–to–Output Skew

Same Frequency

(Note 8.)

Diff Frequency

Same Frequency

Diff Frequency

200

300

300

450

300

400

400

600

ps

fmax ≤ 100MHz

fmax ≤ 100MHz

fmax > 100MHz

fmax > 100MHz

fVCO

VCO Lock Range

Power_Dn = 0

Power_Dn = 1

200

100

480

240

MHz

fmax

Maximum Output Frequency

Qa, Qb (

÷2)

Qa, Qb, Qc (

÷4)

Qc (

÷6)

150

120

80

MHz

Note 9.

tpd

Reference to EXT_FB Average Delay

TCLK

PECL_CLK

–150

–400

0

–250

+150

–100

ps

fref = 50MHz; FB = ÷8;

Note 12.

tpw

Output Duty Cycle (Note 8.)

tCYCLE/2

–750

tCYCLE/2

±500

tCYCLE/2

+750

ps

tr, tf

Output Rise/Fall Time (Note 8.)

0.1

1.0

ns

0.8 to 2.0V

tPLZ, tPHZ

Output Disable Time

2.0

8.0

ns

50

Ω to VCC/2

tPZL

Output Enable Time

2.0

10

ns

50

Ω to VCC/2

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

±100

ps

Note 10.

tlock

Maximum PLL Lock Time

10

ms

8. Measured with 50

Ω to VCC/2 termination.

9. fmax limited by skew spec. Outputs will generate valid CMOS signals up to 180MHz.

10. See Applications Info section for more jitter information.

11. Input reference frequency is bounded by VCO lock range and feedback divide selection.

12. tpd is specified for 50MHz input reference, the window will shrink/grow proportionally from the minimum limit with shorter/linger reference

periods. The tpd does not include jitter.