MPC930 MPC931

TIMING SOLUTIONS

BR1333 — Rev 6

7

MOTOROLA

MPC930

Figure 5. Dual Frequency Configuration

Div_Sela

‘0’

Div_Selb

‘1’

Div_Selc

‘0’

ExtFB_Sel

‘0’

Input Ref

16.66MHz

66.66MHz (Processor)

Qa

33.33MHz (PCI)

Qb

33.33MHz (PCI)

Qc

2

2

2

MPC930

Figure 6. Single Frequency Configuration

Div_Sela

‘1’

Div_Selb

‘1’

Div_Selc

‘0’

ExtFB_Sel

‘0’

Input Ref

16.66MHz

33.33MHz

Qa

33.33MHz

Qb

33.33MHz

Qc

2

2

2

MPC931

Figure 7. “Zero” Delay Fractional Multiplier

Div_Sela

‘1’

Div_Selb

‘1’

Div_Selc

‘1’

ExtFB_Sel

‘1’

Input Ref

33.33MHz

50MHz

Qa

50MHz

Qb

33.33MHz

Qc

2

2

2

Figure 8. “Zero” Delay Fractional Divider

Ext_FB

1

MPC931

Div_Sela

‘0’

Div_Selb

‘1’

Div_Selc

‘1’

ExtFB_Sel

‘1’

Input Ref

50MHz

100MHz

Qa

50MHz

Qb

33.33MHz

Qc

2

2

2

Ext_FB

1

MPC931

Figure 9. “Zero” Delay Multiply by 3 (50% Duty Cycle)

Div_Sela

‘0’

Div_Selb

‘0’

Div_Selc

‘1’

ExtFB_Sel

‘1’

Input Ref

33.33MHz

100MHz

Qa

100MHz

Qb

33.33MHz

Qc

2

2

2

Figure 10. “Zero” Delay Divide by 3 (50% Duty Cycle)

Ext_FB

1

MPC931

Div_Sela

‘0’

Div_Selb

‘0’

Div_Selc

‘1’

ExtFB_Sel

‘1’

Input Ref

100MHz

100MHz

Qa

100MHz

Qb

33.33MHz

Qc

2

2

2

Ext_FB

1

Using the MPC930/931 as a Zero Delay Buffer

The external feedback option of the MPC930/931 clock

driver allows for its use as a zero delay buffer. By using one of

the outputs as a feedback to the PLL the propagation delay

through the device is eliminated. The PLL works to align the

output edge with the input reference edge thus producing a

near zero delay. The Tpd of the device is specified in the

specification tables. For zero delay buffer applications, the

MPC931 is recommended over the MPC930. The MPC931

has been optimized and specified specifically for use as a

zero delay buffer.

When used as a zero delay buffer the MPC930/931 will

likely be in a nested clock tree application. For these

applications the MPC931 offers a LVPECL clock input as a

PLL reference. This allows the user to use LVPECL as the

primary clock distribution device to take advantage of its far

superior skew performance. The MPC931 then can lock onto

the LVPECL reference and translate with near zero delay to

low skew LVCMOS outputs. Clock trees implemented in this

fashion will show significantly tighter skews than trees

developed from CMOS fanout buffers.

To minimize part–to–part skew the external feedback

option again should be used. The PLL in the MPC931

decouples the delay of the device from the propagation delay

variations of the internal gates. From the specification table

one sees a Tpd variation of only

±150ps, thus for multiple

devices under identical configurations the part–to–part skew

will be around 850ps (300ps for Tpd variation plus 300ps