JS28F128J3C120 datasheet(39/72 Pages) INTEL

39 / 72 page

28F256J3, 28F128J3, 28F640J3, 28F320J3

Datasheet

10.2

Read Identifier Codes

The Read identifier codes operation outputs the manufacturer code, device-code, and the block

lock configuration codes for each block (See Section 9.2, “Device Commands” on page 35 for

details on issuing the Read Device Identifier command). Page-mode reads are not supported in this

read mode. To terminate the operation, write another valid command. Like the Read Array

command, the Read Identifier Codes command functions independently of the VPEN voltage. This

command is valid only when the WSM is off or the device is suspended. Following the Read

Identifier Codes command, the following information can be read.

10.2.1

Read Status Register

The Status Register may be read to determine when a block erase, program, or lock-bit

configuration is complete and whether the operation completed successfully. It may be read only

after the specified time W12 (see Table 9, “Write Operations” on page 26). After writing this

command, all subsequent read operations output data from the Status Register until another valid

command is written. Page-mode reads are not supported in this read mode. The Status Register

contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables

the device (see Table 13, “Chip Enable Truth Table” on page 33). OE# must toggle to VIH or the

device must be disabled before further reads to update the Status Register latch. The Read Status

During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid

until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and

D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check

SR.7), all contents of the Status Register are valid when read.

Table 17. Read Identifier Codes

Code

Address

(1)

Data

Manufacture Code

00000

(00) 89

Device Code

32-Mbit

00001

(00) 16

64-Mbit

00001

(00) 17

128-Mbit

00001

(00) 18

256-Mbit

00001

(00) 1D

Block Lock Configuration

0002(2)

• Block Is Unlocked

D0 = 0

• Block Is Locked

D0 = 1

• Reserved for Future Use

D[7:1]

NOTES:

1. A0 is not used in either x8 or x16 modes when obtaining the identifier

codes. The lowest order address line is A1. Data is always presented

on the low byte in x16 mode (upper byte contains 00h).

2. X selects the specific block’s lock configuration code.

3. D[7:1] are invalid and should be ignored.

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