JS28F128J3C120 datasheet(29/72 Pages) INTEL

номер детали	JS28F128J3C120

подробное описание детали	Intel StrataFlash짰 Memory

PDF	72 Pages

Scroll/Zoom	100%

производитель	INTEL [Intel Corporation]

домашняя страница	http://www.intel.com

Logo

29 / 72 page

28F256J3, 28F128J3, 28F640J3, 28F320J3

Datasheet

7.4

Reset Operation

NOTE: STS is shown in its default mode (RY/BY#).

7.5

AC Test Conditions

NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and

output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.

Figure 14. AC Waveform for Reset Operation

)

Table 11. Reset Specifications

Sym

Parameter

Min

Max

Unit

Notes

tPLPH

RP# Pulse Low Time

(If RP# is tied to VCC, this specification is not

applicable)

µs

1,2

tPHRH

RP# High to Reset during Block Erase, Program, or

Lock-Bit Configuration

100

1,3

NOTES:

1. These specifications are valid for all product versions (packages and speeds).

2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not

executing then the minimum required RP# Pulse Low Time is 100 ns.

3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until

outputs are valid.

Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V

Output

Test Points

Input

CCQ/2

CCQ

0.0

CCQ/2

JS28F128J3C120 датащи(PDF) 29 Page - Intel Corporation

JS28F128J3C120 датащи(HTML) 29 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL