SSM2160/SSM2161

–10–

REV. 0

Serial Data Input Format

The standard format for data sent to SSM2160 is an address

byte followed by a data byte. This is depicted in the truth table,

Figure 19. Two 8-bit bytes are required for each Master and

each of the six channel updates. The first byte sent contains the

address and is identified by the MSB being logic high. The

second byte contains the data and is identified by the MSB being

logic low. The 7 LSBs of the first data byte set the attenuation level

from 0 dB to –127 dB for the Master. The 5 LSBs of the byte set

the Channel gain levels from 0 dB to 31 dB.

Serial Data Control Inputs

The SSM2160 provides a simple 3- or 4-wire serial interface—

see the timing diagram in Figure 1. Data is presented to the

DATA pin and the serial clock to the CLK pin. Data may be

shifted in at rates up to 1 MHz (typically).

The shift register, CLK, is enabled when the WRITE input is

low. The WRITE thus serves as a Chip Select input; however,

the shift register contents are not transferred to the holding

register until the rising edge of LD. In most cases, WRITE and

LD

will be tied together, forming a tradition 3-wire serial interface.

To enable a data transfer, the WRITE and LD inputs are driven

logic low. The 8-bit serial data, formatted MSB first, is input on

the DATA pin and clocked into the shift register on the falling

edge of CLK. The data is latched on the rising edge of WRITE

and LD.

Table III. Input/Output Levels vs. Attenuation/Gain

Input

Gain/Loss

Output

dBu

mV rms

Master

Channel

Net dBu

mV rms

0

775

–31

31

0

0

775

–31

22

0

31

31

0

775

–28

31

0

31

31

3

1100

Saturation Prevention

Unlike a passive potentiometer, the SSM2160 can give up to

+31 dB of gain, thereby creating a potential for saturating the

VCAs, resulting in an undesirable clipping or overload condi-

tion. Careful choice of input signal levels and digital gain

parameters will eliminate the possibility. A few of the many

acceptable gain and attenuation settings that keep the signals

within the prescribed limits are shown in Table III. The

input and output levels are given in mV rms and dBu (0 dBu

= 0.775 V rms).

Line one of the table: the master is not allowed to have less than

–31 dB attenuation, and the channel is allowed +31 dB of gain.

Since the net gain is zero, there is no possibility of overload with

the expected maximum input signal.

Line two of the table shows that input signal limited to –31 dBu

will allow +31 dB of Channel gain and 0 dB of Master attenua-

tion. With an input below –31 dBu, the output will never

exceed 0 dBu, so no overloading is possible.

Line Three of the table allows an input of –28 dBu, Master

attenuation of 0 dB, and 31 dB Channel gain. The output is a

maximum of 3 dBu (1.1 V rms), which is acceptable for power

supplies of

±6 V or more. So long as V p-p < V

will be no overloading (See Table I).

If unity overall gain is required from the SSM2160, there should

be no net gain between the master (loss) and channel (gain),

with both at their lowest attenuation position. Minimum

channel gain is recommended for minimum distortion.

MASTER

DAC

CHANNEL

DAC

IN

OUT

SUMMATION

RESISTOR

“R”

i

SIGNAL

V+

C

EXTERNAL

SSM2160

Figure 20. VCA Control Scheme

Control Range and Channel Tracking

Each Channel VCA is controlled by its own DAC’s output, plus

the control signal from the master DAC. This is shown in

Figure 21. Channel DACs are configured to increase the gain of

the VCA in 1 dB steps from zero to 31 dB. Thus, the midpoint

(15, or 16 if you prefer) should be chosen as the center setting

of the electronic balance controls. Since the master DAC feeds

all summation nodes, the attenuation of all VCAs simulta-

neously change from 0 dB to the noise floor.

Maximum Attenuation of all channels occurs when the Master is

set to –127 dB attenuation, and the Channel is set to 0 dB gain.

Minimum Attenuation of all channels occurs when the Master is

set at 0 dB, and the Channel is set to +31 dB.

Once the channel to channel balance has been set, the Master

may be changed without changing the balance. This is shown

graphically in Figure 21.

+31

+16

0

–16

–32

–48

–64

–80

–96

–112

–128

0 0 0 0 0

1 1 1 1 1

0 0 0 0 0

1 1 1 1 1

CHANNEL

GAIN

CHANNEL

GAIN

CHANNEL

GAIN

MASTER

ATTENUATION

+31

+16

0

+31

+16

0

NOISE FLOOR

0 0 0 0 0 0

NET GAIN/ATTEN

1 1 1 1 1 1

Figure 21. Practical Control Range

Master/Channel Step Sizes

The details of the DAC control of the Channel VCAs is

depicted in Figure 20. A 7-bit current output DAC and an op

amp converts the digitally commanded master control level to

an analog voltage. A capacitor across the feedback resistor

limits the rate of change at the output to prevent clicking. A

5-bit DAC converts the digitally commanded channel control

level to a voltage via a resistor R. These two control signals sum

in resistor R and are fed to the channel VCA. Although we