ADMC200

REV. B

–11–

DESCRIPTION OF THE REGISTERS

All unspecified register locations are reserved.

SYSCTRL

System Control Register (See Table V and VI)

SYSSTAT

System Status Register (See Table VII)

ADCU

These registers contain the results from the first

ADCV

three analog input channels U, V, and W. The

ADCW

output data format is twos complement and

therefore Bit 0 is always zero as the A/D

converter has 11-bit resolution.

ADCAUX

This register contains the conversion result

of the auxiliary channel.

PWMTM

PWM Master Switching Period

PWMCHA

PWM Channel A on-time

PWMCHB

PWM Channel B on-time

PWMCHC

PWM Channel C on-time

PWMDT

PWM Programmable Deadtime Value

PWMPD

PWM Programmable Pulse Deletion Value

ID/IQ

These are the results of the reverse rotation

(torque and flux components).

PHV1/2/3

These are the results from the forward

Clarke Transformation.

PHIP1/2/3

The inputs for reverse vector transformation

(Clarke and Park).

IX/IY

These registers contain the results of the Clarke

transformation that are the inputs to the reverse

Park rotation.

VX, VY

VX , VY contain the results of the forward

Park rotation.

RHOP

RHOP is the angle used during the forward vec-

tor transformation. Writing to the RHOP regis-

ter causes the forward rotation to start based on

values in RHOP, VD and VQ registers.

RHO

RHO is the angle used during the reverse vector

transformation. Writing to this register starts

the reverse rotation using the values in the

RHO, PHIP1/2/3 registers.

RHO and RHOP are unsigned ratios of 360

°.

For example, 45 degrees would be 45/360

Table IV. Read Registers

Name

Register Function

ID/PHV1/VX

0000

°

IQ/PHV2

0001

°

IX/PHV3

0010

Reverse Clarke Cos + 0

°/Forward Result Cos +240°

IY/VY

0011

Reverse Clarke Cos +90

°/Forward Cos +90°

0100

Reserved

ADCV

0101

A/D Conversion Result Channel V

ADCW

0110

A/D Conversion Result Channel W

ADCAUX

0111

A/D Conversion Result Auxiliary Channel

ADCU

1000

A/D Conversion Result Channel U

1001

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

SYSCTRL

1101

System Control

SYSSTAT

1110

System Status

1111

Reserved

Table V. System Control (SYSCTRL) Registers

RESET

Bit

Function

Default

0

Reserved, Must Be 0

0

1

Reserved, Must Be 0

0

3

Enables U Channel Conversion

(1 = Enable) Three/Three-Phase Mode

0

4

Enables AUX Channel Conversion

(0 = Disable, 1 = Enable)

0

5

Divide External Clock by 2

(0 = No, 1 = Yes)

0

6

Park Interrupt Enable

0

7

ADC Interrupt Enable

(0 = Disable, 1 = Enable)

0

8

IRQ Pin Format (Edge or Level Based

Interrupt Requests) (0 = Edge)

0

10

Reverse Rotation (0 = 2/3, 1 = 3/3)

Forward Rotation (1 = Enable)

0

Bit 0, 1 Reserved for future use. Always write 0 to these bits.

Bit 3

Channel U Conversion Enable. If Bit 3 is set to 1, then

Channel U will be converted along with V, W and/or

AUX. This bit selects three-/three-phase mode.

Bit 4

Aux Channel Conversion Enable. If Bit 4 is set to

1, then the AUX input will be converted along with

the channels V, W and/or U.

Bit 5

If Bit 5 = 1, then the external clock will be divided by

two to derive the system clock. If the external clock

frequency is greater than 12.5 MHz, then this bit must

be set.

Bit 6

Park Interrupt Enable. This bit allows interrupts to

be generated when the Park rotation is completed.

Bit 7

ADC Interrupt Enable. This bit allows interrupts to

be generated via the

IRQ pin when the analog-to-

digital conversion process is complete.