ADMC200

REV. B

–9–

completion. When an interrupt occurs, the user must check Bit

1 of the system status register, SYSSTAT, to determine if the

vector transformation block was the source of the interrupt.

During the vector transformation, the transformation registers

must not be written to or the vector rotation results will be invalid.

Forward Park Rotation

formation can be described by:

the inputs to the reverse Clarke transformation.

Forward Clarke Transformation (2 to 3 Phase)

The second operation to be applied to the above results, is the

Forward Clarke Transformation where 2 phase (stator) voltage

signals are converted to 3 phase (stator) voltage signals.

For the inverse Clarke transform we require three phase out-

puts of the form below:

PHV1

V cos

α

PHV2

V cos (

α + 120)

PHV3

V cos (

α + 240)

We have two quadrature voltages (V cos

α and V sinα) available.

PHV2

V cos (

1

2 ×

V cos

α – 3

2 ×

V sin

α

PHV3

V cos (

1

2 ×

V cos

α+ 3

2 ×

V sin

α

INTERRUPT GENERATION

There are two interrupt sources on the ADMC200 that may be

independently enabled to generate interrupts. The first

interrupt source is the Analog Input Block, which, if enabled,

generates an interrupt at the end of conversion. The second in-

terrupt source is the Vector Transformation Block, which,

if enabled, generates an interrupt at the end of a Vector

Transformation.

When a 1 is stored in Bit 7 of the SYSCTRL register, ADC

interrupts are enabled. When a 1 is stored in Bit 6 of the

SYSCTRL register, Vector Transformation interrupts are en-

abled. Upon a reset of the chip, both bits are set to the default

condition, 0, thus disabling all interrupts.

When an enabled interrupt occurs, Bit 11 of the SYSSTAT

register becomes a 1. If that interrupt had been an ADC inter-

rupt, Bit 0 of SYSSTAT register would also be set to 1. If that

interrupt had been a Vector Transformation interrupt, Bit 1 of

SYSSTAT would be set to 1. Whenever the SYSSTAT register

is read, these three bits go back to their default state, 0, immedi-

ately after their values are loaded onto the data bus. Upon a re-

set, these three bits also go to their default state, 0.

The

IRQ pin has an open-drain driver, which will drive it low at

the appropriate times, but the user must supply an external

pull-up resistor to bring the node back high when it is not being

pulled low.

The

IRQ pin operates in one of two modes, edge mode or level

mode. In edge mode, when an enabled interrupt occurs, the

IRQ pin will be driven low for one system clock period. In level

mode, when an enable interrupt occurs, the

IRQ pin will be

driven low, and will remain low until the SYSSTAT register is

read. The combination of level mode and the open-drain driver

allows multiple interrupt sources in an application to drive a

single interrupt input line on the host DSP or microprocessor.

Edge mode or level mode is determined with Bit 8 of the

SYSCTRL register. Edge mode (0) is the default; a 1 in this bit

will put the

IRQ pin into level mode.

The recommended method of using the interrupt generation

capability is to set edge or level mode, enable the appropriate

interrupts, and then monitor the

IRQ line. After the IRQ pin

goes low, the SYSSTAT register of the ADMC200 should be

read, (1) to determine if it was this chip that caused the inter-

rupt, if other lines are wired together with this

IRQ pin, and (2)

if it was this chip, to determine if it was generated by the Analog

Input Block or the Vector Transformation Block. Once this

is done, the appropriate interrupt handling routine may be

executed.

APPLICATION NOTE LIST

1. AN-407 AC Motor Control Experiments Using the ADMC200

Evaluation Board

2. AN-408 AC Motor Control Using the ADMC200 Motion

Coprocessor

3. AN-409 Advanced Motor Control Techniques Using the

ADMC200 Motion Coprocessor

POWER SUPPLY CONNECTIONS AND SETUP

± 5%.

(32) and both AGND pins (27, 28) should be star point con-

nected at a point close to the AGND pins of the ADMC200.

The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should

also be connected to AGND pins close to the ADMC200.

Power supplies should be decoupled at the power pins using a

0.1

µF capacitor. A 220 nF capacitor must also be connected as

close as possible between REFIN (Pin 33) and SGND (Pin 32).

In addition, the

IRQ requires a 15 K pull-up to the V

DSP/CONTROLLER INTERFACE

The ADMC200 has a 12 bit bidirectional parallel port for inter-

facing with Analog Devices’ ADSP-2100 DSP family or micro-

controllers/microprocessors.

The ADMC200 coprocessor is designed to be conveniently in-

terfaced to ADI’s family of fixed-point DSPs. Figures 11 and 12

show the interfacing between the ADMC200 and the ADSP-

2101/2105/2115, ADSP-2171, ADSP-2181, TMS320C2x

DSPs. In the case of the TMS320C2x, some glue logic is re-

quired to decode the RD/

WR lines and invert the CLKOUT1

signal.

The ADSP-2101/2105/2115 CLKOUT frequency equals the

crystal/clock frequency of its CLKIN. This signal (CLKOUT)

can be used to directly drive the CLK line (Pin 21) on the

ADMC200. The ADMC200 coprocessor can be operated with

a clock frequency between the range of 6.25 MHz and 25 MHz.

If the clock frequencies are greater than 12.5 MHz, then it is

necessary to internally divide down the external clock to derive

the ADMC200’s system clock (via SYSCTRL register).