ADF4113BCP datasheet(10/24 Pages) AD

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CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 24. SW1 and SW2

are normally-closed switches. SW3 is normally-open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

BUFFER

TO R COUNTER

REFIN

100k

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 24. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 25. It is followed by a

2-stage limiting ampliﬁer to generate the CML (Current Mode

Logic) clock levels needed for the prescaler.

AVDD

AGND

500

1.6V

BIAS

GENERATOR

RFINA

RFINB

Figure 25. RF Input Stage

PRESCALER (P/P+1)

The dual-modulus prescaler (P/P+1), along with the A and B

counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF input stage and divides it

down to a manageable frequency for the CMOS A and B counters.

The prescaler is programmable. It can be set in software to 8/9,

16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL feed-

back counter. The counters are specified to work when the

prescaler output is 200 MHz or less. Thus, with an RF input

frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a

value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

fVCO = [(P

× B) + A] × fREFIN/R

fVCO

Output frequency of external voltage controlled oscilla-

tor (VCO).

Preset modulus of dual modulus prescaler

Preset Divide Ratio of binary 13-bit counter (3 to 8191).

Preset Divide Ratio of binary 6-bit swallow counter (0 to

63).

fREFIN Output frequency of the external reference frequency

oscillator.

Preset divide ratio of binary 14-bit programmable refer-

ence counter (1 to 16383).

R COUNTER

The 14-bit R counter allows the input reference frequency to be

divided down to produce the reference clock to the phase fre-

quency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

13-BIT B

COUNTER

6-BIT A

COUNTER

PRESCALER

P/P + 1

FROM RF

INPUT STAGE

MODULUS

CONTROL

N = BP + A

LOAD

TO PFD

Figure 26. A and B Counters

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE

PUMP

The PFD takes inputs from the R counter and N counter

(N = BP + A) and produces an output proportional to the phase

and frequency difference between them. Figure 27 is a simpli-

ﬁed schematic. The PFD includes a programmable delay element

which controls the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and minimizes phase noise and reference spurs. Two bits in the

Reference Counter Latch, ABP2 and ABP1 control the width

of the pulse. See Table III.

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