ADF4116 datasheet(20/20 Pages) AD

20 / 20 page

ADF4116/ADF4117/ADF4118

–20–

REV. 0

ADuC812 Interface

Figure 29 shows the interface between the ADF4116 family and

the ADuC812 microconverter. Since the ADuC812 is based on

an 8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4116 family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the microconverter to the device. When the third

byte has been written the LE input should be brought high to

complete the transfer.

SCLOCK

MOSI

I/O PORTS

ADuC812

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4116/

ADF4117/

ADF4118

Figure 29. ADuC812 to ADF4116 Family Interface

On ﬁrst applying power to the ADF4116 family, it needs three

writes (one each to the R counter latch, the N counter latch and

the initialization latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT conﬁgured as

lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK

rate of the ADuC812 is 4 MHz. This means that the maximum

rate at which the output frequency can be changed will be 166 kHz.

ADSP-2181 Interface

Figure 30 shows the interface between the ADF4116 family and

the ADSP-21xx Digital Signal Processor. The ADF4116 family

needs a 21-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

Autobuffered Transmit Mode of operation with Alternate Fram-

ing. This provides a means for transmitting an entire block of

serial data before an interrupt is generated.

SCLK

I/O FLAGS

ADSP-21xx

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4116/

ADF4117/

ADF4118

TFS

Figure 30. ADSP-21xx to ADF4116 Family Interface

Set up the word length for 8 bits and use three memory loca-

tions for each 24-bit word. To program each 21-bit latch, store

the three 8-bit bytes, enable the Autobuffered mode and then

write to the transmit register of the DSP. This last operation

initiates the autobuffer transfer.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Chip Scale

(CP-20)

BOTTOM VIEW

(ROTATED 180 )

0.014 (0.35)

45°

0.018 (0.45)

0.016 (0.40)

0.014 (0.35)

0.079 (2.0) REF

0.079

(2.0)

REF

DETAIL E

0.020 (0.5) REF

LEAD PITCH

0.0079 (0.20)

REF

0.0083 (0.211)

0.0079 (0.200)

0.0077 (0.195)

SEATING

PLANE

0.039 (1.00)

0.035 (0.90)

0.031 (0.80)

0.159 (4.05)

0.157 (4.00)

0.156 (3.95)

TOP VIEW

0.159 (4.05)

0.157 (4.00)

0.156 (3.95)

0.0059 (0.15)

REF

0.011 (0.275)

0.010 (0.250)

0.009 (0.225)

0.0059

(0.15)

REF

0.018 (0.45)

0.016 (0.40)

0.014 (0.35)

LEAD OPTION

DETAIL E

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

Thin Shrink Small Outline

(RU-16)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.201 (5.10)

0.193 (4.90)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

0.0433 (1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

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