ADF4116/ADF4117/ADF4118

–17–

REV. 0

The Initialization Latch

When C2, C1 = 1, 1 then the Initialization Latch is programmed.

This is essentially the same as the Function Latch (programmed

when C2, C1 = 1, 0).

However, when the Initialization Latch is programmed there is a

additional internal reset pulse applied to the R and N counters.

This pulse ensures that the N counter is at load point when the

N counter data is latched and the device will begin counting in

close phase alignment.

If the Latch is programmed for synchronous power-down (CE

pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse and

so close phase alignment is maintained when counting resumes.

When the first N counter data is latched after initialization, the

internal reset pulse is again activated. However, successive N

counter loads after this will not trigger the internal reset pulse.

Device Programming After Initial Power-Up

After initially powering up the device, there are three ways to

program the device.

Initialization Latch Method

Program the Initialization Latch (“11” in 2 LSBs of input word).

Make sure that F1 bit is programmed to “0.” Then do an R load

(“00” in 2 LSBs). Then do an N load (“01” in 2 LSBs). When the

Initialization Latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, N and timeout counters to

load state conditions and also three-states the charge pump.

Note that the prescaler bandgap reference and the oscillator

input buffer are unaffected by the internal reset pulse,

allowing close phase alignment when counting resumes.

3. Latching the first N counter data after the initialization word

will activate the same internal reset pulse. Successive N loads

will not trigger the internal reset pulse unless there is another

initialization.

The CE Pin Method

Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

Program the Function Latch (10). Program the R Counter

Latch (00). Program the N Counter Latch (01). Bring CE high

to take the device out of power-down. The R and N counter will

now resume counting in close alignment.

Note that after CE goes high, a duration of 1

µs may be required

for the prescaler bandgap voltage and oscillator input buffer bias

to reach steady state.

CE can be used to power the device up and down in order to

check for channel activity. The input register does not need to

be reprogrammed each time the device is disabled and enabled

initially applied.

The Counter Reset Method

Do a Function Latch Load (“10” in 2 LSBs). As part of this,

load “1” to the F1 bit. This enables the counter reset. Do an R

Counter Load (“00” in 2 LSBs). Do an N Counter Load (“01”

in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs). As

part of this, load “0” to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initial-

ization method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump, but does not trigger synchronous

power-down. The counter reset method requires an extra func-

tion latch load compared to the initialization latch method.