ADF4116/ADF4117/ADF4118

–16–

REV. 0

THE FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch will be pro-

grammed. Table VI shows the input data format for programming

the Function Latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this is “1,” the R counter

and the A, B counters are reset. For normal operation this bit

should be “0.” Upon powering up, the F1 bit needs to be disabled,

the N counter resumes counting in “close” alignment with the R counter.

(The maximum error is one prescaler cycle.)

Power-Down

DB3 (PD1) and DB19 (PD2) on the ADF4116 family, provide

programmable power-down modes. They are enabled by the

CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2, PD1.

In the programmed asynchronous power-down, the device pow-

ers down immediately after latching a “1” into bit PD1, with the

condition that PD2 has been loaded with a “0.”

In the programmed synchronous power-down, the device power

down is gated by the charge pump to prevent unwanted fre-

quency jumps. Once the power-down is enabled by writing a

“1” into bit PD1 (on condition that a “1” has also been loaded

to PD2), then the device will go into power-down after the first

successive charge pump event.

When a power down is activated (either synchronous or asynchro-

nous mode including CE-pin-activated power down), the

following events occur:

All active dc current paths are removed.

The R, N and timeout counters are forced to their load state

conditions.

The charge pump is forced into three-state mode.

The digital clock detect circuitry is reset.

The oscillator input buffer circuitry is disabled.

The input register remains active and capable of loading and

latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the

ADF4116 family. Table VI shows the truth table.

Phase Detector Polarity

DB7 (F2) of the function latch sets the Phase Detector Polarity.

When the VCO characteristics are positive this should be set to

“1.” When they are negative it should be set to “0.”

Charge Pump Three-State

This bit puts the charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

Fastlock Enable Bit

DB9 of the Function Latch is the Fastlock Enable Bit. Only

when this is “1” is Fastlock enabled.

Fastlock Mode Bit

DB11 of the Function Latch is the Fastlock Mode bit. When

Fastlock is enabled, this bit determines which Fastlock Mode is

used. If the Fastlock Mode bit is “0” then Fastlock Mode 1 is

selected and if the Fastlock Mode bit is “1,” then Fastlock

Mode 2 is selected.

If Fastlock is not enabled (DB9 = “0”), then DB11 (ADF4116)

same as that programmed to DB11.

Fastlock Mode 1

to a low state and the charge pump current is switched to the

filter and ensure stability while in Fastlock by altering the loop

bandwidth.

The device enters Fastlock by having a “1” written to the CP

Gain bit in the N register. The device exits Fastlock by having a

“0” written to the CP Gain bit in the N register.

Fastlock Mode 2

to a low state and the charge pump current is switched to the high

ensure stability while in Fastlock by altering the loop bandwidth.

The device enters Fastlock by having a “1” written to the CP

Gain bit in the N register. The device exits Fastlock under the

control of the Timer Counter. After the timeout period deter-

mined by the value in TC4–TC1, the CP Gain bit in the N

register is automatically reset to “0” and the device reverts to

normal mode instead of Fastlock.

Timer Counter Control

In the ADF4116 family, the user has the option of switching

between two charge pump current values to speed up locking to

a new frequency.

When using the Fastlock feature with the ADF4116 family, the

normal sequence of events is as follows:

The user must make sure that Fastlock is enabled. Set DB9 of the

ADF4116 family to “1.” The user must also choose which Fastlock

Mode to use. As discussed in the previous section, Fastlock

Mode 2 uses the values in the Timer Counter to determine the

timeout period before reverting to normal mode operation after

Fastlock. Fastlock Mode 2 is chosen by setting DB11 of the

ADF4116 family to “1.”

The user must also decide how long they want the high current

(1 mA) to stay active before reverting to low current (250

µA).

This is controlled by the Timer Counter Control Bits DB14 to

DB11 (TC4–TC1) in the Function Latch. The truth table is

given in Table VI.

Now, when the user wishes to program a new output frequency,

they can simply program the A, B counter latch with new values

for A and B. At the same time they can set the CP Gain bit to a

“1,” which sets the charge pump 1 mA for a period of time deter-

mined by TC4–TC1. When this time is up, the charge pump

current reverts to 250

µA. At the same time the CP Gain Bit in

the A, B Counter latch is reset to 0 and is now ready for the

next time that the user wishes to change the frequency again.