ADDC02803SC/ADDC02805SA

REV. A

–12–

Potential System Instability: The preceding analysis assumes

dc voltages and currents. For ac waveforms the incremental

input model for the POL converter must also include the effects

of its input filter and control loop dynamics. When the POL

converter is connected to a power source, modeled as a voltage

ADI DC/DC CONVERTER

INPUT

TERMINALS

Figure 33. Model of Power Source and POL Converter

Connection

The network shown in Figure 33 is second order and has the

following characteristic equation:

sL

L

C

s

LL

R

RC

SP

SP

N

SP

2

10

()

()

–||

++

+

+









+=

For the power delivery to be efficient, it is required that

relationship must hold:

CR

LL

R

R

LL

CR

PN

SP

S

S

SP

PN

||

()

or

()

||

>

+

>

+

too small, the system might be unstable. This condition would

first be observed at low input line and full load since the abso-

If an instability results and it cannot be corrected by changing

LISN requirement, one possible solution is to place a capacitor

across the input of the POL converter. Another possibility is to

place a small resistor in series with this extra capacitor.

The analysis has so far assumed the source of power was a volt-

age source (e.g., a battery) with some source impedance. In

some cases, this source may be the output of a front-end (FE)

converter. Although each FE converter is different, a model for

a typical one would have an LC output filter driven by a voltage

source whose value was determined by the feedback loop. The

LC filter usually has a high Q, so the compensation of the feed-

back loop is chosen to help dampen any oscillations that result

from load transients. In effect, the feedback loop adds “positive

resistance” to the LC network.

When the POL converter is connected to the output of this FE

converter, the POL’s “negative resistance” counteracts the

effects of the FE’s “positive resistance” offered by the feedback

loop. Depending on the specific details, this might simply mean

that the FE converter’s transient response is slightly more oscil-

latory, or it may cause the entire system to be unstable.

mately 1

µH and C

µF. Figures 13 and 14

show a more accurate depiction of the input impedance of the

converter as a function of frequency. The negative resistance is,

itself, a very good incremental model for the power state of the

converter for frequencies into the several kHz range.

NAVMAT DERATING

NAVMAT is a Navy power supply reliability manual frequently

cited by specifiers of power supplies. A key section of NAVMAT

P4855-1A discusses guidelines for derating designs and their

components. The two key derating criteria are voltage derating

and power derating. Voltage derating is done to reduce the possi-

bility of electrical breakdown, whereas power derating is done to

maintain the component material below a specified maximum

temperature. While power deratings are typically stated in terms

of current limits (e.g., derate to x% of maximum rating), NAVMAT

also specifies a maximum junction temperature of the semicon-

ductor devices in a power supply. The NAVMAT component

deratings applicable to the ADDC02805SA and ADDC02803SC

are as follows:

Resistors

80% voltage derating

50% power derating

Capacitors

50% voltage and ripple voltage derating

70% ripple current derating

Transformers and Inductors

60% continuous voltage and current derating

90% surge voltage and current derating

20

°C less than rated core temperature

30

°C below insulation rating for hot spot temperature

25% insulation breakdown voltage derating

40

°C maximum temperature rise

Transistors

50% power derating

60% forward current (continuous) derating

75% voltage and transient peak voltage derating

110

°C maximum junction temperature

Diodes (Switching, General Purpose, Rectifiers)

70% current (surge and continuous) derating

65% peak inverse voltage derating

110

°C maximum junction temperature

Diodes (Zeners)

70% surge current derating

60% continuous current derating

50% power derating

110

°C maximum junction temperature

Microcircuits (Linears)

70% continuous current derating

75% signal voltage derating

110

°C maximum junction temperature

The ADDC02803SC and ADDC02805SA can meet all the

derating criteria listed above. There are, however, a few areas of

the NAVMAT deratings where meeting the guidelines unduly

sacrifices performance of the circuit. The standard unit therefore

makes the following exceptions.

Common-Mode EMI Filter Capacitors: The standard sup-

ply uses 500 V capacitors to filter common-mode EMI. NAVMAT

guidelines would require 1000 V capacitors to meet the 50%

voltage derating (500 V dc input to output isolation), resulting

in less common-mode capacitance for the same space. In typi-

cal electrical power supply systems, where the load ground is

eventually connected to the source ground, common-mode

voltages never get near the 500 V dc rating of the standard