AD9884ASLASHPCB datasheet(15/24 Pages) AD

15 / 24 page

REV. B

AD9884A

–15–

In typical PC-based graphic systems, the sync signals are simply

TTL-level drivers feeding unshielded wires in the monitor

cable. Since the AD9884A operates from a 3.3 V power supply,

and TTL sources may drive a high level to 5 V or more, it is

recommended that a 1 k

Ω series current-limiting resistor be placed

in series with HSYNC and COAST. If these pins are driven

more than 0.5 V outside the power supply voltages, internal

ESD protection diodes will conduct, and may dissipate consid-

erable power if the sync source is of particularly low impedance.

If a signal is applied to the AD9884A when the IC’s power is

off, then even a 1 V signal can turn on the ESD protection

diodes. The 1 k

Ω series resistor will protect the device from

overstress in this situation as well.

Serial Control Port

The serial control port (SDA, SCL) is designed for 3.3 V logic.

If there are 5 V drivers on the bus, these pins should be pro-

tected with 150

Ω series resistors.

OUTPUT SIGNAL HANDLING

The digital outputs are designed and specified to operate from a

3.3 V power supply (VDD). They can also work with a VDD as

low as 2.5 V for compatibility with other 2.5 V logic.

CLAMPING

To properly digitize the incoming signal, the dc offset of the

input signal must be adjusted to fit the range of the on-board

A/D converters.

Most graphic systems produce RGB signals with black at ground

and white at approximately +0.75 V. However, if sync signals

are embedded in the graphics, then the sync tip is often at ground

potential, and black is at +300 mV. Then white is at approxi-

mately +1.0 V. Some common RGB line amplifier boxes use

emitter-follower buffers to split signals and increase drive capa-

bility. This introduces a 700 mV dc offset to the signal which

must be removed for proper capture by the AD9884A.

The key to clamping is to identify a portion (time) of the signal

when the graphic system is known to be producing black. An

offset is then introduced which results in the A/D converters

producing a black output (code 00h) when the known black

input is present. That offset then remains in place when other

signal levels are processed, and the entire signal is shifted to

eliminate offset errors.

In most graphic systems, black is transmitted between active

video lines. Going back to CRT displays, when the electron

beam has completed writing a horizontal line on the screen (at

the right side), the beam is deflected quickly to the left side of

the screen (called horizontal retrace) and a black signal is pro-

vided to prevent the beam from disturbing the image.

In systems with embedded sync, a blacker-than-black signal

(HSYNC) is produced briefly to signal the CRT that it is time

to begin a retrace. For obvious reasons, it is important to avoid

clamping on the tip of HSYNC. Fortunately, there is virtually

always a period following HSYNC called the back porch where

a good black reference is provided. This is the time when clamp-

ing should be done.

The clamp timing can be established by simply exercising the

CLAMP pin at the appropriate time (with EXTCLMP = 1).

The polarity of this signal is set by the CLAMPOL bit.

A simpler method of clamp timing employs the AD9884A inter-

nal clamp timing generator. Register CLPLACE is programmed

with the number of pixel times that should pass after the trailing

edge of HSYNC before clamping starts. A second register

(CLDUR) sets the duration of the clamp. These are both 8-bit

values, providing considerable flexibility in clamp generation.

The clamp timing is referenced to the trailing edge of HSYNC

because, though HSYNC duration can vary widely, the back

porch (black reference) always follows HSYNC. A good start-

ing point for establishing clamping is to set CLPLACE to 08h

(providing 8 pixel periods for the graphics signal to stabilize

after sync) and set CLDUR to 14h (giving the clamp 20 pixel

periods to reestablish the black reference).

Clamping is accomplished by placing an appropriate charge on

the external input coupling capacitor. The value of this capaci-

tor affects the performance of the clamp. If it is too small, there

will be a significant amplitude change during a horizontal line

time (between clamping intervals). If the capacitor is too large,

then it will take excessively long for the clamp circuit to recover

from a large change in incoming signal offset. The recommended

value results in recovering from a step error of 100 mV to within

1/2 LSB in 10 lines with a clamp duration of 20 pixels on a

60 Hz SXGA signal.

GAIN AND OFFSET CONTROL

The AD9884A can accommodate input signals with inputs

ranging from 0.5 V to 1.0 V full scale. The full-scale range is set

in three 8-bit registers (REDGAIN, GRNGAIN, BLUGAIN).

A code of 0 in a gain register establishes a minimum input range

of 0.5 V; 255 corresponds with the maximum range of 1.0 V.

Note that INCREASING the gain setting results in an image

with LESS contrast.

The offset control shifts the entire input range, resulting in a

change in image brightness. Three 6-bit registers (REDOFST,

GRNOFST, BLUOFST) provide independent settings for each

channel.

The offset controls provide a

±31 LSB adjustment range. This

range is connected with the full-scale range, so if the input range

is doubled (from 0.5 V to 1.0 V) then the offset step size is also

doubled (from 2 mV per step to 4 mV per step).

Figure 8 illustrates the interaction of gain and offset controls.

The magnitude of an LSB in offset adjustment is proportional

to the full-scale range, so changing the full-scale range also

changes the offset. The change is minimal if the offset setting is

near midscale. When changing the offset, the full-scale range is

not affected, but the full-scale level is shifted by the same amount

as the zero scale level.

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