AD9884ASLASHPCB datasheet(12/24 Pages) AD

12 / 24 page

REV. B

AD9884A

–12–

CLOCK GENERATOR CONTROL

7–3

PHASE

Clock Phase Adjust

A five-bit value that adjusts the sampling phase in 32 steps across

one pixel time. Each step represents an 11.25 degree shift in

sampling phase.

The power-up default value is PHASE = 16.

6–5

VCORNGE

VCO Range Select

Two bits that establish the operating range of the clock generator.

VCORNGE

Range (MHz)

20-60

50-90

80-120

110-140

VCORNGE must be set to correspond with the desired operat-

ing frequency (incoming pixel rate).

The power-up default value is VCORNGE = 01.

4–2

CURRENT

Charge Pump Current

Three bits that establish the current driving the loop filter in the

clock generator.

CURRENT

Current ( A)

000

001

100

010

150

011

250

100

350

101

500

110

750

111

1500

CURRENT must be set to correspond with the desired operat-

ing frequency (incoming pixel rate).

The power-up default value is CURRENT = 001.

OUTPHASE

Output Port Phase

One bit that determines whether even pixels or odd pixels go to

Port A.

OUTPHASE

First Pixel After HSYNC

Port A

Port B

In normal operation (OUTPHASE = 0), when operating in

Dual Channel output mode (DEMUX = 1), the first sample

after the HSYNC leading edge is presented at Port A. Every

subsequent ODD sample appears at Port A. All EVEN samples

go to Port B.

When OUTPHASE = 1, these ports are reversed and the first

sample goes to Port B.

When DEMUX = 0, this bit is ignored.

When reading back the value of OUTPHASE, the bit appears at

3–1

REVID

Silicon Revision ID

The die revision of the AD9884A can be determined by reading

these three bits.

Serial Control Port

A 2-wire serial control interface is provided. Up to four AD9884A

devices may be connected to the 2-wire serial interface, with

each device having a unique address.

The 2-wire interface comprises a clock (SCL) and a bidirec-

tional data (SDA) pin. The Analog Flat Panel Interface acts as a

slave for receiving and transmitting data over the serial interface.

When the serial interface is not active, the logic levels on SCL

and SDA are pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA

must change only when SCL is LOW. If SDA changes state

while SCL is HIGH, the serial interface interprets that action as

a start or stop sequence.

There are six components to serial bus operation:

• Start Signal

• Slave Address Byte

• Base Register Address Byte

• Data Byte to Read or Write

• Stop Signal

When the serial interface is inactive (SCL and SDA are HIGH)

communications are initiated by sending a start signal. The start

signal is a HIGH-to-LOW transition on SDA while SCL is

HIGH. This signal alerts all slaved devices that a data transfer

sequence is coming.

The first eight bits of data transferred after a start signal com-

prising a seven bit slave address (the first seven bits) and a

single R/

W bit (the eighth bit). The R/W bit indicates the direc-

tion of data transfer, read from (1) or write to (0) the slave

device. If the transmitted slave address matches the address of

the device (set by the state of the SA1-0 input pins in Table IV),

the AD9884A acknowledges by bringing SDA LOW on the

ninth SCL pulse. If the addresses do not match, the AD9884A

does not acknowledge.

Table IV. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(MSB)

(LSB)

1100

1101

1110

1111

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9884A does not acknowledge the master device during

a write sequence, the SDA remains HIGH so the master can

generate a stop signal. If the master device does not acknowl-

edge the AD9884A during a read sequence, the AD9884A inter-

prets this as “end of data.” The SDA remains HIGH so the

master can generate a stop signal.

AD9884A/PCB датащи(PDF) 12 Page - Analog Devices

AD9884A/PCB датащи(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL