AD7864

–12–

REV. A

Reading After the Conversion Sequence

Figure 8 shows the same conversion sequence as Figure 7. In

this case, however, the results of the four conversions (on VIN1

to VIN4) are read after all conversions have finished, i.e., when

BUSY goes logic low. The FRSTDATA signal goes logic high

at the end of the first conversion just prior to

EOC going logic

low. As mentioned previously FRSTDATA has an indetermi-

nate state after initial power up, therefore FRSTDATA may

already be logic high. Unlike the case when reading between

each conversion the output data register pointer is incremented

on the rising edge of

RD because the next conversion result is

available. This means FRSTDATA will go logic low after the

first rising edge on

RD.

Successive read operations will access the remaining conversion

results in an ascending channel order. Each read operation

increments the output data register pointer. The read operation

that accesses the last conversion result causes the output data

register pointer to be reset so that the next read operation will

access the first conversion result again. This is shown in Figure

8 with the fifth read after BUSY goes low accessing the result of

the conversion on VIN1. Thus the output data registers act as a

circular buffer in which the conversion results may be continu-

ally accessed. The FRSTDATA signal will go high when the

first conversion result is available.

Data is enabled onto the data bus DB0 to DB11 using

CS and

RD. Both CS and RD have the same functionality as described

in the previous section. There are no restrictions or perfor-

mance implications associated to the position of the read opera-

tions after BUSY goes low. The only restriction is that there is

minimum time between read operations. Notice also that a

“Quiet Time” is needed before the start of the next conversion.

Using an External Clock

The logic input

INT/EXT CLK allows the user to operate the

AD7864 using the internal clock oscillator or an external clock.

The optimum performance is achieved by using the internal

clock on the AD7864. The highest external clock frequency

allowed is 5 MHz. This means a conversion time of 2.6

µs

compared to 1.65

µs using the internal clock. In some instances,

however, it may be useful to use an external clock when high

throughput rates are not required. For example, two or more

AD7864s may be synchronized by using the same external clock

for all devices. In this way there is no latency between output

logic signals like

EOC due to differences in the frequency of the

internal clock oscillators. Figure 9 shows how the various logic

outputs are synchronized to the CLK signal. Each conversion

requires 14 clocks. The output data register pointer is reset to

point to the first register location on the falling edge of the 12

clock cycle of the first conversion in the conversion sequence—

See Accessing the Output Data Registers. At this point the logic

output FRSTDATA goes logic high. The result of the first

conversion is transferred to the output data registers on the

falling edge of the 13 clock cycle. The FRSTDATA signal is

reset on the falling edge of the 13 clock cycle of the next

conversion, i.e., when the result of the second conversion is

transferred to its output data register. As mentioned previously,

the pointer is incremented by the rising edge of the

RD signal if

the result of the next conversion is available. The

EOC signal

goes logic low on the falling edge of the 13 clock cycle and is

reset high again on the falling edge of the 14 clock cycle.

QUIET

TIME

DATA

CONVST

BUSY

EOC

FRSTDATA

RD

CS

Figure 8. Timing Diagram, Reading After the Conversion Sequence