AD7864AS-2 datasheet(4/19 Pages) AD

4 / 19 page

AD7864

–4–

REV. A

TIMING CHARACTERISTICS1, 2

Parameter

A, B Versions

Units

Test Conditions/Comments

tCONV

1.65

µs max

Conversion Time, Internal Clock

Clock Cycles

Conversion Time, External Clock

2.6

µs max

CLKIN = 5 MHz

tACQ

0.34

µs max

Acquisition Time

tBUSY

No. of Channels

Selected Number of Channels Multiplied by

x (tCONV + t9) – t9

µs max

(tCONV + EOC Pulsewidth)—EOC Pulsewidth

tWAKE-UP—External VREF

µs max

STBY Rising Edge to CONVST Rising Edge

tWAKE-UP—Internal VREF

6ms max

STBY Rising Edge to CONVST Rising Edge

ns min

CONVST Pulsewidth

ns min

CONVST Rising Edge to BUSY Rising Edge

Read Operation

ns min

CS to RD Setup Time

ns min

CS to RD Hold Time

ns min

Read Pulsewidth

ns max

Data Access Time After Falling Edge of

RD, V

DRIVE = 5 V

ns max

Data Access Time After Falling Edge of

RD, V

DRIVE = 3 V

ns min

Bus Relinquish Time After Rising Edge of

ns max

ns min

Time Between Consecutive Reads

ns min

EOC Pulsewidth

180

ns max

t10

ns max

RD Rising Edge to FRSTDATA Edge (Rising or Falling)

t11

ns max

EOC Falling Edge to FRSTDATA Falling Delay

t12

ns min

EOC to RD Delay

Write Operation

t13

ns min

WR Pulsewidth

t14

ns min

CS to WR Setup Time

t15

ns min

WR to CS Hold Time

t16

ns min

Input Data Setup Time of Rising Edge of

t17

ns min

Input Data Hold Time

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

2See Figures 7, 8 and 9.

3Refer to the Standby Mode Operation section. The MAX specification of 6 ms is valid when using a 0.1

µF decoupling capacitor on the V

REF pin.

4Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V.

5These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

(VD = +5 V

5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications

TMIN to TMAX unless otherwise noted.)

OUTPUT

50pF

1.6V

400 A

1.6mA

Figure 1. Load Circuit for Access Time and Bus Relinquish Time

AD7864AS-2 датащи(PDF) 4 Page - Analog Devices

AD7864AS-2 датащи(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL