AD7864

–10–

REV. A

AD7864-3

Figure 4 shows the analog input section of the AD7864-3. The

analog input range is

±2.5 V on the V

input can be left unconnected but if it is connected to a poten-

tial then that potential must be AGND.

2.5V

REFERENCE

T/H

TO ADC

REFERENCE

CIRCUITRY

6k

R2

TO INTERNAL

COMPARATOR

AD7864-3

R1

Figure 4. AD7864-3 Analog Input Structure

For the AD7864-3, R1 = 6 k

Ω and R2 = 6 kΩ. As a result, the

resistor input stage is followed by the high input impedance

stage of the track/hold amplifier.

The designed code transitions take place midway between

successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs,

etc.) LSB size is given by the formula, 1 LSB = FSR/4096.

Output coding is 2s complement binary with 1 LSB = FSR/

4096 = 5 V/4096 = 1.22 mV. The ideal input/output transfer

function for the AD7864-3 is shown in Table III.

Table III. Ideal Input/Output Code Table for the AD7864-3

Analog Input

l

Digital Output Code Transition

011 . . . 110 to 011 . . . 111

+FSR/2 – 5/2 LSB

011 . . . 101 to 011 . . . 110

+FSR/2 – 7/2 LSB

011 . . . 100 to 011 . . . 101

AGND + 3/2 LSB

000 . . . 001 to 000 . . . 010

AGND + 1/2 LSB

000 . . . 000 to 000 . . . 001

AGND – 1/2 LSB

111 . . . 111 to 000 . . . 000

AGND – 3/2 LSB

111 . . . 110 to 111 . . . 111

–FSR/2 + 5/2 LSB

100 . . . 010 to 100 . . . 011

–FSR/2 + 3/2 LSB

100 . . . 001 to 100 . . . 010

–FSR/2 + 1/2 LSB

100 . . . 000 to 100 . . . 001

NOTES

±2.5 V - AD7864-3) with V

SELECTING A CONVERSION SEQUENCE

Any subset of the four channels VIN1 to VIN4 can be selected

for conversion. The selected channels are converted in an

ascending order. For example if the channel selection includes

VIN4, VIN1 and VIN3 then the conversion sequence will be

VIN1, VIN3 and then VIN4. The conversion sequence selection

my be made by using either the hardware channel select input

pins (SL1 through SL4) or programming the channel select

register. A logic high on a hardware channel select pin (or logic

one in the channel select register) when

CONVST goes logic

high, marks the associated analog input channel for inclusion in

the conversion sequence.

Figure 5 shows the arrangement used. The

H/S SEL controls a

multiplexer which selects the source of the conversion sequence

information, i.e., from the Hardware channel select pins (SL1 to

SL4) or from the channel selection register. When a conversion

is started the output from the multiplexer is latched until the

end of the conversion sequence. The data bus Bits DB0 to DB3

(DB0 representing Channel 1 through DB3 representing Chan-

nel 4) are bidirectional and become inputs to the channel select

register when

RD is logic high and CS and WR are logic low.

The logic state on DB0 to DB3 is latched into the channel select

register when

WR goes logic high.

M

U

L

T

I

P

L

E

X

E

R

DATA BUS

D0

D1

D2

D3

WR

CS

WR

CHANNEL SELECT

REGISTER

SL1

SL2

SL3

SL4

HARDWARE CHANNEL

SELECT PINS

H/S

LATCH

SEQUENCER

TRANSPARENT WHILE WAITING FOR

CONVST. LATCHED ON THE RISING

EDGE OF

CONVST AND DURING A

CONVERSION SEQUENCE.

SELECT INDIVIDUAL

TRACK-AND-HOLDS

FOR CONVERSION

Figure 5. Channel Select Inputs and Registers

RD

WR

CS

DATA

DATA IN

Figure 6. Channel Selection via Software Control