SSL4120 datasheet(16/48 Pages) NXP

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SSL4120

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Product data sheet

Rev. 2 — 1 November 2012

16 of 48

NXP Semiconductors

SSL4120

Resonant power supply controller IC with PFC for LED lighting

7.7 PFC controller

The PFC controller converts the rectified universal mains voltage into an accurately

regulated Vboost of 400 V (DC) or 450 V (DC). It operates in Quasi-Resonant (QR) or

Discontinuous Conduction Mode (DCM) and is controlled using an on-time control

system. The resulting mains harmonic current emissions of a typical application can meet

the Class-C MHR requirements for lighting applications.

The PFC controller uses valley switching to minimize losses. A primary stroke is only

started once the previous secondary stroke ends and the voltage across the PFC

MOSFET reaches a minimum value.

7.7.1 PFC gate driver (GATEPFC pin)

The circuit driving the gate of the power MOSFET has a high current sourcing capability

Isource(GATEPFC) of 500 mA. It also has a high current sink capability Isink(GATEPFC) of 1.2 A.

The source and sink capabilities enable fast power MOSFET switch-on and switch-off to

ensure efficient operation. The driver is supplied from the regulated SUPREG supply.

7.7.2 PFC on-time control

The PFC operates under on-time control. The following determine the PFC MOSFET

on-time:

• the error amplifier and the loop compensation using the COMPPFC pin voltage

– At Vton(COMPPFC)zero = 3.5 V, the on-time is reduced to zero.

– At Vton(COMPPFC)max = 1.25 V, the on-time is at a maximum

• Mains compensation using the SNSMAINS pin voltage

The on-time must be modulated with the mains voltage to reach the Class-C MHR

requirements. In the application, this is achieved when a modulation current is injected

into the COMPPFC network using a capacitor which connects to the mains voltage, see

Figure 19.

7.7.2.1

PFC error amplifier (COMPPFC and SNSBOOST pins)

Vboost is divided using a high-ohmic resistive divider. It is supplied to the SNSBOOST pin.

The transconductance error amplifier, which compares the SNSBOOST voltage with an

accurate trimmed reference voltage Vreg(SNSBOOST), is connected to this pin. The external

loop compensation network on the COMPPFC pin filters the output current. In a typical

application, a resistor and two capacitors set the regulation loop bandwidth.

The COMPPFC voltage is clamped at a maximum of Vclamp(COMPPFC). This clamp avoids a

long recovery time if Vboost rises above the regulation level for a period.

7.7.2.2

PFC mains compensation (SNSMAINS pin)

The mathematical equation for the transfer function of a power factor corrector contains

the square of the mains input voltage. In a typical application, this results in a low

bandwidth for low mains input voltages. At high mains input voltages, the MHR

requirements are hard to meet.

The SSL4120 contains a correction circuit to compensate for this effect. The average

mains voltage is measured using the SNSMAINS pin and this information is supplied to an

internal compensation circuit.

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