AD73322AST datasheet(25/43 Pages) AD

25 / 43 page

AD73322

–25–

REV. B

In a single AD73322 configuration, each 16-bit data frame sent

from the DSP to the device is interpreted as DAC data, but it is

necessary to send two DAC words per sample period in order to

ensure DAC update. Also, as the device count setting defaults

to 1, it must be set to 2 (001b) to ensure correct update of both

DACs on the AD73322.

Appendix B details the initialization and operation of an AD73322

in normal Data Mode.

SDOFS

SCLK

SDO

SDIFS

SDI

ADC SAMPLE WORD (DEVICE 2)

ADC SAMPLE WORD (DEVICE 1)

DAC DATA WORD (DEVICE 2)

DAC DATA WORD (DEVICE 1)

Figure 16. Interface Signal Timing for Data Mode

Operation

Mixed Program/Data Mode

This mode allows the user to send control words to the device

along with the DAC data. This permits adaptive control of the

device whereby control of the input/output gains etc., can be

affected by interleaving control words along with the normal

flow of DAC data. The standard data frame remains 16 bits, but

now the MSB is used as a flag bit to indicate whether the re-

maining 15 bits of the frame represent DAC data or control

information. In the case of DAC data, the 15 bits are loaded

with MSB justification and LSB set to 0 to the DAC register.

Mixed mode is enabled by setting the MM bit (CRA:1) to 1 and

the DATA/PGM bit (CRA:0) to 1. In the case where control

setting changes will be required during normal operation, this

mode allows the ability to load both control and data informa-

tion with the slight inconvenience of formatting the data. Note

that the output samples from the ADC will also have the MSB

set to zero to indicate it is a data word.

Appendix C details the initialization and operation of an AD73322

operating in mixed mode. Note that it is not essential to load

the control registers in Program Mode before setting mixed

mode active. It is also possible to initiate mixed mode by pro-

gramming CRA with the first control word and then interleaving

control words with DAC data.

Digital Loop-Back

This mode can be used for diagnostic purposes and allows the

user to feed the ADC samples from the ADC register directly to

the DAC register. This forms a loop-back of the analog input to

the analog output by reconstructing the encoded signal using

the decoder channel. The serial interface will continue to work,

which allows the user to control gain settings, etc. Only when

DLB is enabled with mixed mode operation can the user disable

the DLB, otherwise the device must be reset.

SPORT Loop-Back

This mode allows the user to verify the DSP interfacing and

connection by writing words to the SPORT of the devices and

have them returned back unchanged after a delay of 16 SCLK

cycles. The frame sync and data word that are sent to the device

are returned via the output port. Again, SLB mode can only be

disabled when used in conjunction with mixed mode, otherwise

the device must be reset.

Analog Loop-Back

In Analog Loop-Back mode, the differential DAC output is

connected, via a loop-back switch, to the ADC input (see Figure

17). This mode allows the ADC channel to check functionality

of the DAC channel as the reconstructed output signal can be

monitored using the ADC as a sampler. Analog Loop-Back is

enabled by setting the ALB bit (CRF:7).

NOTE: Analog Loop-Back can only be enabled if the Analog

Gain Tap is powered down (CRC:1 = 0).

INVERTING

OP AMPS

ANALOG

LOOP-BACK

SELECT

INVERT

SINGLE-

ENDED

ENABLE

GAIN

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

VREF

VFBN1

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

REFERENCE

0/38dB

PGA

AD73322

VREF

ANALOG GAIN

TAP POWERED

DOWN

Figure 17. Analog Loop-Back Connectivity

AD73322AST датащи(PDF) 25 Page - Analog Devices

AD73322AST датащи(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

датащи скачать

ссылки URL