AD73322AST datasheet(14/43 Pages) AD

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AD73322

–14–

REV. B

GAIN

INVERT

SINGLE-ENDED

ENABLE

0/38dB

PGA

DECIMATOR

SERIAL

I/O

PORT

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

1-BIT

DAC

SWITCHED

CAPACITOR

LOW-PASS

FILTER

DIGITAL

SIGMA-

DELTA

MODULATOR

GAIN

INTER-

POLATOR

VREF

VFBN1

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

DECIMATOR

+6/–15dB

CONTINUOUS

TIME

LOW-PASS

FILTER

1-BIT

DAC

SWITCHED

CAPACITOR

LOW-PASS

FILTER

DIGITAL

SIGMA-

DELTA

MODULATOR

GAIN

INTER-

POLATOR

VREF

VFBN2

VINN2

VINP2

VFBP2

VOUTP2

VOUTN2

AD73322

AGND1

AGND2

DGND

SDOFS

SDO

MCLK

RESET

SCLK

SDIFS

SDI

DVDD

AVDD2

AVDD1

REFERENCE

PGA

ANALOG

SIGMA-DELTA

MODULATOR

ANALOG

LOOP

BACK

GAIN

INVERT

SINGLE-ENDED

ENABLE

0/38dB

PGA

ANALOG

SIGMA-DELTA

MODULATOR

ANALOG

LOOP

BACK

Figure 9. Functional Block Diagram

FUNCTIONAL DESCRIPTION

Encoder Channels

Both encoder channels consist of a pair of inverting op amps

with feedback connections that can be bypassed if required, a

switched capacitor PGA and a sigma-delta analog-to-digital

converter (ADC). An on-board digital filter, which forms part of

the sigma-delta ADC, also performs critical system-level filter-

ing. Due to the high level of oversampling, the input antialias

requirements are reduced such that a simple single pole RC

stage is sufficient to give adequate attenuation in the band of

interest.

Programmable Gain Amplifier

Each encoder section’s analog front end comprises a switched

capacitor PGA, which also forms part of the sigma-delta modu-

lator. The SC sampling frequency is DMCLK/8. The PGA,

whose programmable gain settings are shown in Table IV, may

be used to increase the signal level applied to the ADC from low

output sources such as microphones, and can be used to avoid

placing external amplifiers in the circuit. The input signal level

to the sigma-delta modulator should not exceed the maximum

input voltage permitted.

The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)

in control register D.

Table IV. PGA Settings for the Encoder Channel

IGS2

IGS1

IGS0

Gain (dB)

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