SDA datasheet(16/29 Pages) EXAR

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Rev. 1.0.1

mostly on the board design and on the

manufacturer and construction details of the

components. Proper selection of components

can reduce the sound to very low levels. In

general Ultrasonic Mode is not used unless

required as it reduces light load efficiency.

Ultrasonic Mode

Ultrasonic mode is an extension of PFM to

ensure that the switching frequency never

enters the audible range. When this mode is

entered, the switching frequency is set to

30kHz and the duty cycle of the upper and

lower FETs, which are fixed in PFM mode, are

decreased as required to keep the output

voltage in regulation while maintaining the

30kHz switching frequency.

Under extremely light or zero load currents,

the GH on time pulse width can decrease to its

minimum width. When this happens, the lower

FET on time is increased slightly to allow a

small amount of reverse inductor to flow back

into Vin to keep the output voltage in

regulation while maintaining the switching

frequency above the audio range.

Oversampling OVS Mode

Oversampling (OVS) mode is a feature added

the

XRP7724

improve

transient

responses. This mode can only be enabled

when the channel switching frequency is

operating in 1x frequency mode. In OVS mode

the output voltage is sampled 4 times per

switching cycle and is monitored by the AFE

window comparator. If the voltage goes

outside the set high or low limits, the OVS

control electronics can immediately modify the

pulse width of the GH or GL drivers to respond

accordingly, without having to wait for the

next cycle to start. OVS has two types of

response depending on whether the high limit

is exceeded during an unloading transient

(Over Voltage), or the low limit is exceeded

during a loading transient (Under Voltage).

Under Voltage OVS: If there is an increasing

current load step, the output voltage will drop

until the regulator loop adapts to the new

conditions to return the voltage to the correct

level. Depending on where in the switching

cycle the load step happens there can be a

delay of up to one switching cycle before the

control loop can respond. With OVS enabled if

output voltage drops below the lower level, an

immediate GH pulse will be generated and

sent to the driver to increase the output

inductor current toward the new load level

without having to wait for the next cycle to

begin. If the output voltage is still below the

lower limit at the beginning of the next cycle,

OVS will work in conjunction with the PID to

insert additional GH pulses to quickly return

the output voltage back within its regulation

band. The result of this system is transient

response capabilities on par or exceeding

those of a constant on-time control loop.

Over Voltage OVS: When there is a step load

current decrease, the output voltage will

increase (bump up) as the excess inductor

current that is no longer used by the load,

flows into the output capacitors causing the

output voltage to rise.

The voltage will

continue to rise until the inductor current

decreases to the new load current. With OVS

enabled, if the output voltage exceeds the

high limit of the window comparator, a

blanking pulse is generated to truncate the GH

signal.

This

causes

inductor

current

immediately begin decreasing to the new load

level. The GH will continue to be blanked until

the output voltage falls below the high limit.

Again, since the output voltage is sampled at

four times the switching frequency, over shoot

will be decreased and the time required to get

back

into

the

regulation

band

also

decreased.

OVS can be used in conjunction with both the

PWM and PFM operating modes. When it is

activated it can noticeably decrease output

voltage excursions when transitioning between

PWM and PFM modes.

INTERNAL DRIVERS

The internal high and low gate drivers use

totem pole FETs for high drive capability. They

are powered by two external 5V power pins

(VCCD1-2) and (VCCD3-4), VCCD1-2 powers

the drivers for channels 1 and 2 and VCCD3-4

powers channels 3 and 4. The drivers can be

their power pins to the LDO5 output through

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