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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SDA датащи(PDF) 14 Page - Exar Corporation |
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SDA датащи(HTML) 14 Page - Exar Corporation |
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14 / 29 page  X XR RP P7 77 72 24 4 Q Qu ua ad d C Ch ha an nn ne ell D Diig giitta all P PW WM M/ /P PF FM M P Prro og grra am mm ma ab blle e P Po ow we err M Ma an na ag ge em me en ntt S Sy ys stte em m © 2012 Exar Corporation 14/29 Rev. 1.0.1 THEORY OF OPERATION CHIP ARCHITECTURE REGULATION LOOPS Error Amp AFE ADC Error Register PID DPWM Gate Driver Vref DAC Scalar ÷1,2,4 PFM/ Ultrasonic Vin Feed Forward GHx GLx LXx PWM- PFM Sel Current ADC Window Comp. OVS VFB (VOUTx) Vin (VCC) Vdrive (VCCD)x Fine Adjust AFE Fig 16 XRP7724 Regulation Loops Figure 16 shows a functional block diagram of the regulation loops for an output channel. There are four separate parallel control loops; Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), Ultrasonic, and Over Sampling (OVS). Each of these loops is fed by the Analog Front End (AFE) as shown at the left of the diagram. The AFE consist of an input voltage scalar, a programmable Voltage Reference (Vref) DAC, Error Amplifier, and a window comparator. (Please note that the block diagram shown is simplified for ease of understanding. Some of the function blocks are common and shared by each channel by means of a multiplexer.) PWM Loop The PWM loop operates in Voltage Control Mode (VCM) with optional Vin feed forward based on the voltage at the VCC pin. The reference voltage (Vref) for the error amp is created by a 0.15V to 1.6V DAC that has a 12.5mV resolution. In order to get a full 0.6V to 5.5V output voltage range an input scalar is used to reduce feedback voltages for higher output voltages to bring them within the 0.15V to 1.6V control range. So for output voltages up to 1.6V (low range) the scalar has a gain of 1. For output voltages from 1.6V to 3.2V (mid range) the scalar gain is 1/2 and for voltages greater than 3.2V (high range) the gain is 1/4. This results in the low range having a reference voltage resolution of 12.5mV, mid range of 25mV and the high range having a resolution of 50mV. The error amp has a gain of 4 and compares the output voltage of the scalar to Vref to create an error voltage on its output. This is converted to a digital error term by the AFE ADC which is stored in the error register. The error register has a fine adjust function that can be used to improve the output voltage set point resolution by a factor of 5 resulting in a low range resolution of 2.5mV, mid range resolution of 5mV and a high range resolution of 10mV. The output of the error resister is then used by the Proportional Integral Derivative (PID) controller to manage the loop dynamics. The XRP7724 PID is a 17-bit five coefficient control engine that calculates the correct duty cycle under the various operating conditions and feeds it to the Digital Pulse Width Modulator (DPWM). Besides the normal |
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