ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

25

For example, Duty will be 50±0.3784% (or 50±0.3875% when 32KHz crystal is used)at 1Hz.

Level mode: Frequency in one second may change in the maximum range of ±3.784ms

(±3.875ms when 32KHz crystal is used).

Relation Between Mode Waveforms and CRFG Bit



Pulse mode



Level mode

32Khz Clock Output

The crystal oscillator can generate clock pulses of 32KHz from the

INTRB pin. The pin is changed to

“H” by setting the

CLEN bit to “1”.

* 32KHz clock pulse output will not be affected from settings in the clock adjustment register.

When power ON (XSTP=1), 32KHz clock pulses are output from the

INTRB pin.

Oscillator Halt Sensing

Oscillation halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to

“0” by writing data to the control register 2.Upon oscillator halt sending, the XSTP bit is switched from 0 to

1. This function can be applied to judge clock data validity. When the XSTP bit

is “1”,

XSL,

F6 to F0, CT2, CT1, CT0, AALE, BALE, SL2, SL1,

CLEN and TEST bits are reset to “0”.

*1）

The XSTP bit is set to “1” upon power-on from 0V. Note that any instantaneous power disconnection

may cause operation failure.

*2）

Once oscillation halt has been sensed, the XSTP bit is held at “1” even if oscillation is restarted.

Ensure error-free oscillation half sensing by preventing the following events:

1) Instantaneous disconnection of VDD

2) Condensation on the crystal oscillator

3) Generation of noise on the PCB in the crystal oscillator

4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC