ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

23

Control of the

INTRA (INTRB) Output (flag bit, enable bit, interrupt output select bit)

Of the three output wave forms listed above, interrupt output conditions may be set by setting the flag bit

that monitors output state on the register, the enable bit that enables an output wave form and the output

select bit that selects either

INTRA or INTRB to be output.

Flag bit

Enable bit

Interrupt output select bit （SL2，SL1）

(D5，D4 at EH)

（0，0） （0，1） （1，0） （1，1）

Alarm_A

AAFG

(D1 at

FH)

AALE

(D7 at EH)

INTRA

INTRA

INTRA

INTRA

Alarm_B

BAFG

(D0 at

FH)

BALE

(D6 at EH)

INTRA

INTRB

INTRA

INTRB

Periodic interrupt

CTFG

(D2 at

FH)

Disabled at

CT2=CT1=CT0=0

(D2 to D0 at EH)

INTRA

INTRA

INTRB

INTRB

32KHz clock

output

NO

CLEN

(D3 at FH)

INTRB

INTRB

INTRB

INTRB

* When power ON (XSTP=1) since AALE=BALE=CT2=CT1=CT0=

CLEN=SL2=SL1=0, INTRA=OFF

(“H”) and 32KHz clock pulses are output from the

INTRB pin.

When more than one output waveforms are output from a single output pin, the output will have OR

wave form of negative logic of both.

Alarm Interrupt

For setting an alarm time, designated time such as day-of-the-week, hour or minute should be set to the

alarm registers being AALE（BALE）bit to 0. After that set the AALE（BALE） bit to 1, from this moment

onward when such registered alarm time coincide the value of calendar counter the

INTRA (INTRB)

comes down to “L” (ON). The

INTRA (INTRB) output can be controlled by operating to the AALE (BALE)

and AAFG (BAFG) bits.