PXS20 datasheet(13/119 Pages) FREESCALE

13 / 119 page

Introduction

PXS20 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

•

Loss-of-lock detection for reference and feedback clocks

•

Self-clocked mode (SCM) operation

•

On-chip loop filter

•

Auxiliary FMPLL

— Used for FlexRay due to precise symbol rate requirement by the protocol

— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies

of operation for PWM and timers and jitter-free control

— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in

electric motor control loop

— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than

the system to ensure higher resolution

1.5.15

Main Oscillator

The main oscillator provides these features:

•

Input frequency range 4–40 MHz

•

Crystal input mode

•

External reference clock (3.3 V) input mode

•

FMPLL reference

1.5.16

Internal Reference Clock (RC) Oscillator

The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap

reference voltage. The RC oscillator is the device safe clock.

The RC oscillator provides these features:

•

Nominal frequency 16 MHz

•

±5% variation over voltage and temperature after process trim

•

Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the

FMPLL

•

RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)

in case XOSC fails

1.5.17

Clock, Reset, Power Mode, and Test Control Modules (MC_CGM,

MC_RGM, MC_PCU, and MC_ME)

These modules provide the following:

•

Clock gating and clock distribution control

•

Halt, stop mode control

•

Flexible configurable system and auxiliary clock dividers

•

Various execution modes

— Reset, Idle, Test, Safe

— Various RUN modes with software selectable powered modules

— No stand-by mode implemented (no internal switchable power domains)

1.5.18

Periodic Interrupt Timer Module (PIT)

The PIT module implements the following features:

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