PXS20 datasheet(21/119 Pages) FREESCALE

21 / 119 page

Introduction

PXS20 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

•

Duplicated module to guarantee highest possible diagnostic coverage (check of checker)

•

Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.38

Voltage Regulator / Power Management Unit (PMU)

The on-chip voltage regulator module provides the following features:

•

Single external rail required

•

Single high supply required: nominal 3.3 V for packaged option

— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but

can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower

frequency of operation)

•

All I/Os are at same voltage as external supply (3.3 V nominal)

•

Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal

operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing

feature)

1.5.39

Built-In Self-Test (BIST) Capability

This device includes the following protection against latent faults:

•

Boot-time Memory Built-In Self-Test (MBIST)

•

Boot-time scan-based Logic Built-In Self-Test (LBIST)

•

Run-time ADC Built-In Self-Test (BIST)

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Run-time Built-In Self Test of LVDs

1.5.40

IEEE 1149.1 JTAG Controller (JTAGC)

The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic

when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block

is compliant with the IEEE standard.

The JTAG controller provides the following features:

•

IEEE Test Access Port (TAP) interface with 5 pins:

—TDI

—TMS

—TCK

—TDO

—JCOMP

•

Selectable modes of operation include JTAGC/debug or normal system operation

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5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

—BYPASS

— IDCODE

—EXTEST

—SAMPLE

— SAMPLE/PRELOAD

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3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the

boundary scan register is parameterized to support a variety of boundary scan chain lengths.

•

TAP controller state machine that controls the operation of the data registers, instruction register and associated

circuitry

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