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WM8351 датащи(PDF) 95 Page - Wolfson Microelectronics plc |
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WM8351 датащи(HTML) 95 Page - Wolfson Microelectronics plc |
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95 / 330 page ![]() Production Data WM8351 w PD, April 2012, Rev 4.5 95 DSP/PCM Mode B, Master Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 59 DSP/PCM Mode B, Master Mode, with TDM DSP/PCM Mode A, Slave Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 60 DSP/PCM Mode A, Slave Mode with TDM DSP/PCM Mode B, Slave Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) is determined by the selected word length of the interface of the WM8351. Figure 61 DSP/PCM Mode B, Slave Mode, with TDM |
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